Adam Nemet a8e1cda622 [AVX512] Add zero-masking variant to AVX512_masking multiclass ... This completes one item from the todo-list of r215125 "Generate masking instruction variants with tablegen". The AddedComplexity is needed just like for the k variant. Added a codegen test based on valignq. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215173 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-07 23:53:38 +00:00
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Analysis	Remove Support/IncludeFile.h and its only user. This is actively harmful, since	2014-08-07 20:41:17 +00:00
AsmParser
Bitcode
CodeGen	[stack protector] Look through bitcasts to get global variable	2014-08-07 23:08:24 +00:00
DebugInfo
ExecutionEngine	Temporarily Revert "Nuke the old JIT." as it's not quite ready to	2014-08-07 22:02:54 +00:00
IR	Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself.""	2014-08-06 22:30:12 +00:00
IRReader
LineEditor
Linker
LTO
MC	MC: split Win64EHUnwindEmitter into a shared streamer	2014-08-07 02:59:41 +00:00
Object	Add two missing ARM cpusubtypes to the switch statement in	2014-08-07 21:30:25 +00:00
Option
ProfileData
Support	Remove Support/IncludeFile.h and its only user. This is actively harmful, since	2014-08-07 20:41:17 +00:00
TableGen	Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)). No functional changes intended.	2014-08-07 12:07:33 +00:00
Target	[AVX512] Add zero-masking variant to AVX512_masking multiclass	2014-08-07 23:53:38 +00:00
Transforms	Fix for multi-line comment warning	2014-08-07 23:19:55 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile