Adam Nemet a8e1cda622 [AVX512] Add zero-masking variant to AVX512_masking multiclass ... This completes one item from the todo-list of r215125 "Generate masking instruction variants with tablegen". The AddedComplexity is needed just like for the k variant. Added a codegen test based on valignq. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215173 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-07 23:53:38 +00:00
..
AArch64	[stack protector] Look through bitcasts to get global variable	2014-08-07 23:08:24 +00:00
ARM	Make these regexes stricter by disallowing any additional characters in the output.	2014-08-07 23:04:07 +00:00
CPP
Generic	Use "weak alias" instead of "alias weak"	2014-07-30 22:51:54 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	fix materialization of one bit constants and global values which are accessed through	2014-08-07 22:09:01 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Swap arguments and adjust shift count for vsldoi on little endian	2014-08-05 20:47:25 +00:00
R600	R600: Cleanup fadd and fsub tests	2014-08-06 20:27:55 +00:00
SPARC
SystemZ
Thumb	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	[AVX512] Add zero-masking variant to AVX512_masking multiclass	2014-08-07 23:53:38 +00:00
XCore