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58421d7d08
fixes test/Regression/CodeGen/ARM/ret_arg5.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
2.2 KiB
TableGen
60 lines
2.2 KiB
TableGen
//===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
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let Namespace = "ARM";
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
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def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
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def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldr $dst, [$addr]",
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[(set IntRegs:$dst, (load IntRegs:$addr))]>;
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def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
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"str $src, [$addr]",
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[(store IntRegs:$src, IntRegs:$addr)]>;
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def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
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"mov $dst, $src", []>;
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def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
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"mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
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def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
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"add $dst, $a, $b",
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[(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
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