Simon Pilgrim 995b551ae7 [X86][SSE3] Just use an explicit SSE3 target attribute - not a cpu type. ... Merged arch/target into a specific triple - we had i686 and x86_64 targets overriding each other.... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241410 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-05 19:06:32 +00:00
..
AArch64	Fix an overly aggressive assertion in getCopyFromPartsVector.	2015-07-02 23:23:52 +00:00
AMDGPU	Test for specific output in lit test	2015-07-01 22:34:59 +00:00
ARM	llvm/test/CodeGen/ARM/fnattr-trap.ll: Add -mtriple, to appease targeting *-win32.	2015-07-03 08:21:38 +00:00
BPF
CPP
Generic	whitespace tidyup. NFC.	2015-07-03 08:02:12 +00:00
Hexagon
Inputs
Mips
MIR	MIR Serialization: Serialize MBB successors.	2015-06-30 18:16:42 +00:00
MSP430
NVPTX	[NVPTX] expand extload/truncstore for vectors of floats	2015-07-01 21:32:42 +00:00
PowerPC	Add missing builtins to the PPC back end for ABI compliance (vol. 2)	2015-07-05 06:03:51 +00:00
SPARC
SystemZ
Thumb
Thumb2
WinEH	[Verifier] Verify invokes of intrinsics	2015-06-26 21:39:44 +00:00
X86	[X86][SSE3] Just use an explicit SSE3 target attribute - not a cpu type.	2015-07-05 19:06:32 +00:00
XCore