llvm-6502/test/MC/Mips
Toma Tabacu 739ca842aa [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.
Summary:
Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, 
and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8").

We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234406 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-08 13:52:41 +00:00
..
mips1
mips2
mips3
mips4
mips5
mips32
mips32r2
mips32r3
mips32r5
mips32r6
mips64
mips64r2
mips64r3
mips64r5
mips64r6
msa
cfi.s
cpload-bad.s
cpload.s
cpsetup-bad.s
cpsetup.s
do_switch1.s
do_switch2.s
do_switch3.s
eh-frame.s
elf_basic.s
elf_eflags_abicalls.s
elf_eflags_micromips.s
elf_eflags_mips16.s
elf_eflags_nan2008.s
elf_eflags_nanlegacy.s
elf_eflags_noreorder.s
elf_eflags_pic0.s
elf_eflags_pic2.s
elf_eflags.s
elf_reginfo.s
elf_st_other.s
elf-bigendian.ll
elf-gprel-32-64.s
elf-N64.s
elf-relsym.s
elf-tls.s
expr1.s
higher-highest-addressing.s
hilo-addressing.s
lit.local.cfg
llvm-mc-fixup-endianness.s
micromips-16-bit-instructions.s
micromips-alias.s
micromips-alu-instructions.s
micromips-bad-branches.s
micromips-branch-fixup.s
micromips-branch-instructions.s
micromips-control-instructions.s
micromips-diagnostic-fixup.s
micromips-el-fixup-data.s
micromips-expansions.s
micromips-expressions.s
micromips-fpu-instructions.s
micromips-func-addr.s
micromips-invalid.s
micromips-jump26.s
micromips-jump-instructions.s
micromips-label-test-sections.s
micromips-label-test.s
micromips-loadstore-instructions.s
micromips-loadstore-unaligned.s
micromips-movcond-instructions.s
micromips-multiply-instructions.s
micromips-pc16-fixup.s
micromips-relocations.s
micromips-shift-instructions.s
micromips-tailr.s
micromips-trap-instructions.s
mips64-alu-instructions.s
mips64-expansions.s
mips64-instructions.s
mips64-register-names-n32-n64.s
mips64-register-names-o32.s
mips64eb-fixups.s
mips64extins.ll
mips64shift.ll
mips_abi_flags_xx_set.s
mips_abi_flags_xx.s
mips_directives_bad.s
mips_directives.s
mips_gprel16.s
mips-abi-bad.s
mips-alu-instructions.s
mips-bad-branches.s
mips-control-instructions.s
mips-coprocessor-encodings.s
mips-data-directives.s
mips-diagnostic-fixup.s
mips-dsp-instructions.s
mips-expansions-bad.s
mips-expansions.s [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol. 2015-04-08 13:52:41 +00:00
mips-fpu-instructions.s
mips-hwr-register-names.s
mips-jump-delay-slots.s
mips-jump-instructions.s
mips-memory-instructions.s
mips-noat.s
mips-pc16-fixup.s
mips-pdr-bad.s
mips-pdr.s
mips-reginfo-fp32.s
mips-reginfo-fp64.s
mips-register-names-invalid.s
mips-register-names-o32.s
mips-relocations.s
module-directive-bad.s
multi-64bit-func.ll
nabi-regs.s
nacl-mask.s
nooddspreg-cmdarg.s
nooddspreg-error.s
nooddspreg.s
octeon-instructions.s
oddspreg.s
pr11877.s
r-mips-got-disp.s
set-arch.s
set-at-directive-explicit-at.s
set-at-directive.s
set-at-noat-bad-syntax.s
set-defined-symbol.s
set-mips0-directive.s
set-mips16-directive.s
set-mips-directives-bad.s
set-mips-directives.s
set-nodsp.s
set-push-pop-directives-bad.s
set-push-pop-directives.s
sext_64_32.ll
sym-expr.s
sym-offset.ll
unaligned-nops.s
xgot.s