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https://github.com/c64scene-ar/llvm-6502.git
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ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215887 91177308-0d34-0410-b5e6-96231b3b80d8
200 lines
7.0 KiB
C++
200 lines
7.0 KiB
C++
//===-- llvm/MC/MCTargetAsmParser.h - Target Assembly Parser ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCTARGETASMPARSER_H
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#define LLVM_MC_MCTARGETASMPARSER_H
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCParser/MCAsmParserExtension.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include <memory>
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namespace llvm {
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class AsmToken;
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class MCInst;
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class MCParsedAsmOperand;
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class MCStreamer;
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class SMLoc;
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class StringRef;
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template <typename T> class SmallVectorImpl;
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typedef SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>> OperandVector;
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enum AsmRewriteKind {
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AOK_Delete = 0, // Rewrite should be ignored.
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AOK_Align, // Rewrite align as .align.
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AOK_DotOperator, // Rewrite a dot operator expression as an immediate.
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// E.g., [eax].foo.bar -> [eax].8
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AOK_Emit, // Rewrite _emit as .byte.
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AOK_Imm, // Rewrite as $$N.
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AOK_ImmPrefix, // Add $$ before a parsed Imm.
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AOK_Input, // Rewrite in terms of $N.
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AOK_Output, // Rewrite in terms of $N.
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AOK_SizeDirective, // Add a sizing directive (e.g., dword ptr).
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AOK_Skip // Skip emission (e.g., offset/type operators).
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};
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const char AsmRewritePrecedence [] = {
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0, // AOK_Delete
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1, // AOK_Align
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1, // AOK_DotOperator
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1, // AOK_Emit
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3, // AOK_Imm
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3, // AOK_ImmPrefix
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2, // AOK_Input
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2, // AOK_Output
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4, // AOK_SizeDirective
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1 // AOK_Skip
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};
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struct AsmRewrite {
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AsmRewriteKind Kind;
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SMLoc Loc;
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unsigned Len;
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unsigned Val;
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public:
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AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, unsigned val = 0)
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: Kind(kind), Loc(loc), Len(len), Val(val) {}
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};
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struct ParseInstructionInfo {
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SmallVectorImpl<AsmRewrite> *AsmRewrites;
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ParseInstructionInfo() : AsmRewrites(nullptr) {}
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ParseInstructionInfo(SmallVectorImpl<AsmRewrite> *rewrites)
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: AsmRewrites(rewrites) {}
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~ParseInstructionInfo() {}
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};
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/// MCTargetAsmParser - Generic interface to target specific assembly parsers.
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class MCTargetAsmParser : public MCAsmParserExtension {
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public:
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enum MatchResultTy {
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Match_InvalidOperand,
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Match_MissingFeature,
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Match_MnemonicFail,
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Match_Success,
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FIRST_TARGET_MATCH_RESULT_TY
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};
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private:
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MCTargetAsmParser(const MCTargetAsmParser &) LLVM_DELETED_FUNCTION;
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void operator=(const MCTargetAsmParser &) LLVM_DELETED_FUNCTION;
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protected: // Can only create subclasses.
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MCTargetAsmParser();
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/// AvailableFeatures - The current set of available features.
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uint64_t AvailableFeatures;
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/// ParsingInlineAsm - Are we parsing ms-style inline assembly?
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bool ParsingInlineAsm;
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/// SemaCallback - The Sema callback implementation. Must be set when parsing
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/// ms-style inline assembly.
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MCAsmParserSemaCallback *SemaCallback;
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/// Set of options which affects instrumentation of inline assembly.
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MCTargetOptions MCOptions;
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public:
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virtual ~MCTargetAsmParser();
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uint64_t getAvailableFeatures() const { return AvailableFeatures; }
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void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }
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bool isParsingInlineAsm () { return ParsingInlineAsm; }
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void setParsingInlineAsm (bool Value) { ParsingInlineAsm = Value; }
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void setSemaCallback(MCAsmParserSemaCallback *Callback) {
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SemaCallback = Callback;
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}
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virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
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SMLoc &EndLoc) = 0;
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/// ParseInstruction - Parse one assembly instruction.
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///
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/// The parser is positioned following the instruction name. The target
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/// specific instruction parser should parse the entire instruction and
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/// construct the appropriate MCInst, or emit an error. On success, the entire
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/// line should be parsed up to and including the end-of-statement token. On
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/// failure, the parser is not required to read to the end of the line.
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//
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/// \param Name - The instruction name.
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/// \param NameLoc - The source location of the name.
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/// \param Operands [out] - The list of parsed operands, this returns
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/// ownership of them to the caller.
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/// \return True on failure.
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virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc, OperandVector &Operands) = 0;
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/// ParseDirective - Parse a target specific assembler directive
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///
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/// The parser is positioned following the directive name. The target
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/// specific directive parser should parse the entire directive doing or
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/// recording any target specific work, or return true and do nothing if the
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/// directive is not target specific. If the directive is specific for
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/// the target, the entire line is parsed up to and including the
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/// end-of-statement token and false is returned.
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///
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/// \param DirectiveID - the identifier token of the directive.
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virtual bool ParseDirective(AsmToken DirectiveID) = 0;
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/// mnemonicIsValid - This returns true if this is a valid mnemonic and false
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/// otherwise.
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virtual bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) = 0;
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/// MatchAndEmitInstruction - Recognize a series of operands of a parsed
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/// instruction as an actual MCInst and emit it to the specified MCStreamer.
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/// This returns false on success and returns true on failure to match.
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///
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/// On failure, the target parser is responsible for emitting a diagnostic
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/// explaining the match failure.
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virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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uint64_t &ErrorInfo,
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bool MatchingInlineAsm) = 0;
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/// Allows targets to let registers opt out of clobber lists.
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virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
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/// Allow a target to add special case operand matching for things that
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/// tblgen doesn't/can't handle effectively. For example, literal
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/// immediates on ARM. TableGen expects a token operand, but the parser
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/// will recognize them as immediates.
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virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
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unsigned Kind) {
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return Match_InvalidOperand;
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}
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/// checkTargetMatchPredicate - Validate the instruction match against
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/// any complex target predicates not expressible via match classes.
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virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
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return Match_Success;
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}
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virtual void convertToMapAndConstraints(unsigned Kind,
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const OperandVector &Operands) = 0;
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virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
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MCSymbolRefExpr::VariantKind,
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MCContext &Ctx) {
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return nullptr;
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}
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virtual void onLabelParsed(MCSymbol *Symbol) { };
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};
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} // End llvm namespace
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#endif
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