mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a24b7618f8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28841 91177308-0d34-0410-b5e6-96231b3b80d8
179 lines
7.7 KiB
TableGen
179 lines
7.7 KiB
TableGen
//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PowerPC 64-bit instructions. These patterns are used
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// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Fixed point instructions.
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//
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let PPC970_Unit = 1 in { // FXU Operations.
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def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
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def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[]>;
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def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
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"or $rA, $rS, $rB", IntGeneral,
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[]>;
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def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"add $rT, $rA, $rB", IntGeneral,
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[(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
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def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"mulhd $rT, $rA, $rB", IntMulHW,
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[(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
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def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"mulhdu $rT, $rA, $rB", IntMulHWU,
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[(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
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def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
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"cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
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def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
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def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
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def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
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def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"sld $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
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def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"srd $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
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def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
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"srad $rA, $rS, $rB", IntRotateD,
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[(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
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def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
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"extsw $rA, $rS", IntGeneral,
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[(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
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/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
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def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
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"extsw $rA, $rS", IntGeneral,
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[(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
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def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
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"sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
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def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"divd $rT, $rA, $rB", IntDivD,
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[(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
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PPC970_DGroup_First, PPC970_DGroup_Cracked;
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def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"divdu $rT, $rA, $rB", IntDivD,
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[(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
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PPC970_DGroup_First, PPC970_DGroup_Cracked;
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def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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"mulld $rT, $rA, $rB", IntMulHD,
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[(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
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let isTwoAddress = 1, isCommutable = 1 in {
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def RLDIMI : MDForm_1<30, 3,
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(ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
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"rldimi $rA, $rS, $SH, $MB", IntRotateD,
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[]>, isPPC64;
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}
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// Rotate instructions.
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def RLDICL : MDForm_1<30, 0,
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(ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
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"rldicl $rA, $rS, $SH, $MB", IntRotateD,
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[]>, isPPC64;
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def RLDICR : MDForm_1<30, 1,
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(ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
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"rldicr $rA, $rS, $SH, $ME", IntRotateD,
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[]>, isPPC64;
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}
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//===----------------------------------------------------------------------===//
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// Load/Store instructions.
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//
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let isLoad = 1, PPC970_Unit = 2 in {
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def LWA : DSForm_1<58, 2, (ops G8RC:$rT, memrix:$src),
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"lwa $rT, $src", LdStLWA,
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[]>, isPPC64, PPC970_DGroup_Cracked;
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def LD : DSForm_2<58, 0, (ops G8RC:$rT, memrix:$src),
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"ld $rT, $src", LdStLD,
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[]>, isPPC64;
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def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
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"lwax $rD, $src", LdStLHA,
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[(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
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PPC970_DGroup_Cracked;
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def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
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"ldx $rD, $src", LdStLD,
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[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
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}
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
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def STD : DSForm_2<62, 0, (ops G8RC:$rT, memrix:$src),
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"std $rT, $src", LdStSTD,
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[]>, isPPC64;
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def STDX : XForm_8<31, 149, (ops GPRC:$rS, memrr:$dst),
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"stdx $rS, $dst", LdStSTD,
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[]>, isPPC64, PPC970_DGroup_Cracked;
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def STDUX : XForm_8<31, 181, (ops GPRC:$rS, memrr:$dst),
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"stdux $rS, $dst", LdStSTD,
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[]>, isPPC64;
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// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
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def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst),
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"std $rT, $dst", LdStSTD,
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[(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
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def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
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"stdx $rT, $dst", LdStSTD,
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[(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
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PPC970_DGroup_Cracked;
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}
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//===----------------------------------------------------------------------===//
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// Floating point instructions.
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//
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let PPC970_Unit = 3 in { // FPU Operations.
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def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
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"fcfid $frD, $frB", FPGeneral,
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[(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
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def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
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"fctidz $frD, $frB", FPGeneral,
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[(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
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}
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//===----------------------------------------------------------------------===//
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// Instruction Patterns
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//
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// Extensions and truncates to/from 32-bit regs.
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def : Pat<(i64 (zext GPRC:$in)),
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(RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
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def : Pat<(i64 (anyext GPRC:$in)),
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(OR4To8 GPRC:$in, GPRC:$in)>;
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def : Pat<(i32 (trunc G8RC:$in)),
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(OR8To4 G8RC:$in, G8RC:$in)>;
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// SHL/SRL
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def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
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(RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
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def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
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(RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
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