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https://github.com/c64scene-ar/llvm-6502.git
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a98a486ad1
load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
4.9 KiB
TableGen
108 lines
4.9 KiB
TableGen
def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
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def simm12 : Operand<i32> {
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let DecoderMethod = "DecodeSimm12";
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}
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def mem_mm_12 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops GPR32, simm12);
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let EncoderMethod = "getMemEncodingMMImm12";
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let ParserMatchClass = MipsMemAsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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let canFoldAsLoad = 1 in
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class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd> :
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InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
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NoItinerary, FrmI> {
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string Constraints = "$src = $rt";
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}
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class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd>:
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InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
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!strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI>;
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let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
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ADDI_FM_MM<0xc>;
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def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
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ADDI_FM_MM<0x4>;
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def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
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SLTI_FM_MM<0x24>;
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def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
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SLTI_FM_MM<0x2c>;
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def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
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ADDI_FM_MM<0x34>;
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def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
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ADDI_FM_MM<0x14>;
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def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
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ADDI_FM_MM<0x1c>;
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def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
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def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
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def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
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def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
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def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
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def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
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def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
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ADD_FM_MM<0, 0x390>;
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def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IIAlu, and>,
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ADD_FM_MM<0, 0x250>;
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def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IIAlu, or>,
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ADD_FM_MM<0, 0x290>;
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def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>,
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ADD_FM_MM<0, 0x310>;
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def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
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def MULT_MM : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x22c>;
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def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x26c>;
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/// Shift Instructions
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def SLL_MM : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd>,
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SRA_FM_MM<0, 0>;
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def SRL_MM : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd>,
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SRA_FM_MM<0x40, 0>;
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def SRA_MM : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd>,
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SRA_FM_MM<0x80, 0>;
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def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
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SRLV_FM_MM<0x10, 0>;
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def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
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SRLV_FM_MM<0x50, 0>;
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def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
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SRLV_FM_MM<0x90, 0>;
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def ROTR_MM : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd>,
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SRA_FM_MM<0xc0, 0>;
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def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
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SRLV_FM_MM<0xd0, 0>;
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/// Load and Store Instructions - aligned
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def LB_MM : Load<"lb", GPR32Opnd, sextloadi8>, MMRel, LW_FM_MM<0x7>;
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def LBu_MM : Load<"lbu", GPR32Opnd, zextloadi8>, MMRel, LW_FM_MM<0x5>;
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def LH_MM : Load<"lh", GPR32Opnd, sextloadi16>, MMRel, LW_FM_MM<0xf>;
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def LHu_MM : Load<"lhu", GPR32Opnd, zextloadi16>, MMRel, LW_FM_MM<0xd>;
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def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
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def SB_MM : Store<"sb", GPR32Opnd, truncstorei8>, MMRel, LW_FM_MM<0x6>;
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def SH_MM : Store<"sh", GPR32Opnd, truncstorei16>, MMRel, LW_FM_MM<0xe>;
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def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
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/// Load and Store Instructions - unaligned
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def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x0>;
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def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x1>;
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def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x8>;
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def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
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LWL_FM_MM<0x9>;
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}
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