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https://github.com/c64scene-ar/llvm-6502.git
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ddc877ccae
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26653 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.4 KiB
C++
86 lines
2.4 KiB
C++
//===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Alpha implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaInstrInfo.h"
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#include "AlphaGenInstrInfo.inc"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include <iostream>
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using namespace llvm;
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AlphaInstrInfo::AlphaInstrInfo()
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: TargetInstrInfo(AlphaInsts, sizeof(AlphaInsts)/sizeof(AlphaInsts[0])) { }
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bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == Alpha::BIS ||
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oc == Alpha::CPYSS ||
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oc == Alpha::CPYST ||
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oc == Alpha::CPYSSt ||
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oc == Alpha::CPYSTs) {
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// or r1, r2, r2
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// cpys(s|t) r1 r2 r2
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isRegister() &&
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"invalid Alpha BIS instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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return false;
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}
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unsigned
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AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
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switch (MI->getOpcode()) {
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case Alpha::LDL:
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case Alpha::LDQ:
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case Alpha::LDBU:
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case Alpha::LDWU:
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case Alpha::LDS:
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case Alpha::LDT:
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if (MI->getOperand(1).isFrameIndex()) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned
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AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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switch (MI->getOpcode()) {
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case Alpha::STL:
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case Alpha::STQ:
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case Alpha::STB:
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case Alpha::STW:
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case Alpha::STS:
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case Alpha::STT:
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if (MI->getOperand(1).isFrameIndex()) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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