llvm-6502/lib/Target/ARM64
Tim Northover a9a94ce839 TableGen: fix operand counting for aliases
TableGen has a fairly dubious heuristic to decide whether an alias should be
printed: does the alias have lest operands than the real instruction. This is
bad enough (particularly with no way to override it), but it should at least be
calculated consistently for both strings.

This patch implements that logic: first get the *correct* string for the
variant, in the same way as the Matcher, without guessing; then count the
number of whitespace chars.

There are basically 4 changes this brings about after the previous
commits; all of these appear to be good, so I have changed the tests:

+ ARM64: we print "neg X, Y" instead of "sub X, xzr, Y".
+ ARM64: we skip implicit "uxtx" and "uxtw" modifiers.
+ Sparc: we print "mov A, B" instead of "or %g0, A, B".
+ Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208969 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 09:42:04 +00:00
..
AsmParser
Disassembler
InstPrinter TableGen: fix operand counting for aliases 2014-05-16 09:42:04 +00:00
MCTargetDesc
TargetInfo
Utils
ARM64.h
ARM64.td
ARM64AddressTypePromotion.cpp
ARM64AdvSIMDScalarPass.cpp
ARM64AsmPrinter.cpp
ARM64BranchRelaxation.cpp
ARM64CallingConv.h
ARM64CallingConvention.td
ARM64CleanupLocalDynamicTLSPass.cpp
ARM64CollectLOH.cpp
ARM64ConditionalCompares.cpp
ARM64DeadRegisterDefinitionsPass.cpp
ARM64ExpandPseudoInsts.cpp
ARM64FastISel.cpp
ARM64FrameLowering.cpp
ARM64FrameLowering.h
ARM64InstrAtomics.td
ARM64InstrFormats.td TableGen: fix operand counting for aliases 2014-05-16 09:42:04 +00:00
ARM64InstrInfo.cpp
ARM64InstrInfo.h
ARM64InstrInfo.td ARM64: disable printing of swapped compare-mask aliases 2014-05-16 09:41:16 +00:00
ARM64ISelDAGToDAG.cpp [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R. 2014-05-16 09:39:02 +00:00
ARM64ISelLowering.cpp [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R. 2014-05-16 09:39:02 +00:00
ARM64ISelLowering.h [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R. 2014-05-16 09:39:02 +00:00
ARM64LoadStoreOptimizer.cpp
ARM64MachineFunctionInfo.h
ARM64MCInstLower.cpp
ARM64MCInstLower.h
ARM64PerfectShuffle.h
ARM64PromoteConstant.cpp
ARM64RegisterInfo.cpp
ARM64RegisterInfo.h
ARM64RegisterInfo.td
ARM64SchedA53.td
ARM64SchedCyclone.td
ARM64Schedule.td
ARM64SelectionDAGInfo.cpp
ARM64SelectionDAGInfo.h
ARM64StorePairSuppress.cpp
ARM64Subtarget.cpp
ARM64Subtarget.h
ARM64TargetMachine.cpp
ARM64TargetMachine.h
ARM64TargetObjectFile.cpp
ARM64TargetObjectFile.h
ARM64TargetTransformInfo.cpp
CMakeLists.txt
LLVMBuild.txt
Makefile