llvm-6502/test/CodeGen
Eric Christopher a9bd4b4647 Check and allow floating point registers to select the size of the
register for inline asm. This conforms to how gcc allows for effective
casting of inputs into gprs (fprs is already handled).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 00:50:46 +00:00
..
ARM Add a special ARM trap encoding for NaCl. 2013-01-30 16:30:19 +00:00
CPP
Generic
Hexagon
MBlaze
Mips [mips] Test case for r173862. 2013-01-30 00:28:15 +00:00
MSP430
NVPTX
PowerPC PPC QPX requires a 32-byte aligned stack 2013-01-30 23:43:27 +00:00
R600
SI
SPARC
Thumb
Thumb2 FileCheck-ify some grep tests 2013-01-25 22:11:46 +00:00
X86 Check and allow floating point registers to select the size of the 2013-01-31 00:50:46 +00:00
XCore