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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27302 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
5.0 KiB
Plaintext
140 lines
5.0 KiB
Plaintext
//===- README_ALTIVEC.txt - Notes for improving Altivec code gen ----------===//
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Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
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registers, to generate better spill code.
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//===----------------------------------------------------------------------===//
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Altivec support. The first should be a single lvx from the constant pool, the
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second should be a xor/stvx:
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void foo(void) {
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int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
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bar (x);
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}
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#include <string.h>
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void foo(void) {
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int x[8] __attribute__((aligned(128)));
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memset (x, 0, sizeof (x));
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bar (x);
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}
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//===----------------------------------------------------------------------===//
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Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
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When -ffast-math is on, we can use 0.0.
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//===----------------------------------------------------------------------===//
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Consider this:
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v4f32 Vector;
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v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
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Since we know that "Vector" is 16-byte aligned and we know the element offset
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of ".X", we should change the load into a lve*x instruction, instead of doing
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a load/store/lve*x sequence.
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//===----------------------------------------------------------------------===//
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There are a wide range of vector constants we can generate with combinations of
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altivec instructions. Examples
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GCC does: "t=vsplti*, r = t+t" for constants it can't generate with one vsplti
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-0.0 (sign bit): vspltisw v0,-1 / vslw v0,v0,v0
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//===----------------------------------------------------------------------===//
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Missing intrinsics:
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ds*
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mf*
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vavg*
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vmax*
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vmin*
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vmladduhm
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vmr*
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vsel (some aliases only accessible using builtins)
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//===----------------------------------------------------------------------===//
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FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0.
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//===----------------------------------------------------------------------===//
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For functions that use altivec AND have calls, we are VRSAVE'ing all call
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clobbered regs.
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//===----------------------------------------------------------------------===//
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VSPLTW and friends are expanded by the FE into insert/extract element ops. Make
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sure that the dag combiner puts them back together in the appropriate
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vector_shuffle node and that this gets pattern matched appropriately.
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//===----------------------------------------------------------------------===//
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Implement passing/returning vectors by value.
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//===----------------------------------------------------------------------===//
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GCC apparently tries to codegen { C1, C2, Variable, C3 } as a constant pool load
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of C1/C2/C3, then a load and vperm of Variable.
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//===----------------------------------------------------------------------===//
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We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte
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aligned stack slot, followed by a lve*x/vperm. We should probably just store it
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to a scalar stack slot, then use lvsl/vperm to load it. If the value is already
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in memory, this is a huge win.
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//===----------------------------------------------------------------------===//
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Do not generate the MFCR/RLWINM sequence for predicate compares when the
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predicate compare is used immediately by a branch. Just branch on the right
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cond code on CR6.
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//===----------------------------------------------------------------------===//
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SROA should turn "vector unions" into the appropriate insert/extract element
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instructions.
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//===----------------------------------------------------------------------===//
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We need an LLVM 'shuffle' instruction, that corresponds to the VECTOR_SHUFFLE
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node.
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//===----------------------------------------------------------------------===//
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We need a way to teach tblgen that some operands of an intrinsic are required to
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be constants. The verifier should enforce this constraint.
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//===----------------------------------------------------------------------===//
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We should instcombine the lvx/stvx intrinsics into loads/stores if we know that
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the loaded address is 16-byte aligned.
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//===----------------------------------------------------------------------===//
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Instead of writting a pattern for type-agnostic operations (e.g. gen-zero, load,
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store, and, ...) in every supported type, make legalize do the work. We should
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have a canonical type that we want operations changed to (e.g. v4i32 for
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build_vector) and legalize should change non-identical types to thse. This is
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similar to what it does for operations that are only supported in some types,
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e.g. x86 cmov (not supported on bytes).
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This would fix two problems:
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1. Writing patterns multiple times.
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2. Identical operations in different types are not getting CSE'd (e.g.
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{ 0U, 0U, 0U, 0U } and {0.0, 0.0, 0.0, 0.0}.
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//===----------------------------------------------------------------------===//
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Instcombine llvm.ppc.altivec.vperm with an immediate into a shuffle operation.
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//===----------------------------------------------------------------------===//
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Handle VECTOR_SHUFFLE nodes with the appropriate shuffle mask with vsldoi,
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vpkuhum and vpkuwum.
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