llvm-6502/lib/Target/R600/SIRegisterInfo.h
Christian Konig c53270f885 R600/SI: switch back to RegPressure scheduling
Signed-off-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178021 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 14:04:02 +00:00

51 lines
1.4 KiB
C++

//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// \brief Interface definition for SIRegisterInfo
//
//===----------------------------------------------------------------------===//
#ifndef SIREGISTERINFO_H_
#define SIREGISTERINFO_H_
#include "AMDGPURegisterInfo.h"
namespace llvm {
class AMDGPUTargetMachine;
class TargetInstrInfo;
struct SIRegisterInfo : public AMDGPURegisterInfo {
AMDGPUTargetMachine &TM;
const TargetInstrInfo &TII;
SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
virtual BitVector getReservedRegs(const MachineFunction &MF) const;
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
/// \param RC is an AMDIL reg class.
///
/// \returns the SI register class that is equivalent to \p RC.
virtual const TargetRegisterClass *
getISARegClass(const TargetRegisterClass *RC) const;
/// \brief get the register class of the specified type to use in the
/// CFGStructurizer
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
};
} // End namespace llvm
#endif // SIREGISTERINFO_H_