Chad Rosier e5038e191d VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. ... Therefore, rather then generate a pseudo instruction, which is later expanded, generate the necessary instructions in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8		2011-08-20 00:17:25 +00:00
..
Alpha
ARM	VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.	2011-08-20 00:17:25 +00:00
Blackfin
CBackend	Revert r137134. It breaks some code as Eli pointed out.	2011-08-09 18:56:35 +00:00
CellSPU
CPP
Generic
MBlaze
Mips	Use subword loads instead of a 4-byte load when the size of a structure (or a	2011-08-18 23:39:37 +00:00
MSP430
PowerPC
PTX	PTX: Add initial support for device function calls	2011-08-09 17:36:31 +00:00
SPARC
SystemZ
Thumb
Thumb2	Update tests.	2011-08-19 22:19:48 +00:00
X86	Add test case for r138018.	2011-08-19 04:30:24 +00:00
XCore	Add intrinsics for SETEV, GETED, GETET.	2011-08-18 13:00:48 +00:00