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04c559569f
The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
88 lines
2.7 KiB
C++
88 lines
2.7 KiB
C++
//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "R600RegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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using namespace llvm;
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R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm)
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: AMDGPURegisterInfo(tm),
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TM(tm)
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{ RCW.RegWeight = 0; RCW.WeightLimit = 0;}
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BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(AMDGPU::ZERO);
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Reserved.set(AMDGPU::HALF);
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Reserved.set(AMDGPU::ONE);
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Reserved.set(AMDGPU::ONE_INT);
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Reserved.set(AMDGPU::NEG_HALF);
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Reserved.set(AMDGPU::NEG_ONE);
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Reserved.set(AMDGPU::PV_X);
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Reserved.set(AMDGPU::ALU_LITERAL_X);
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Reserved.set(AMDGPU::ALU_CONST);
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Reserved.set(AMDGPU::PREDICATE_BIT);
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Reserved.set(AMDGPU::PRED_SEL_OFF);
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Reserved.set(AMDGPU::PRED_SEL_ZERO);
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Reserved.set(AMDGPU::PRED_SEL_ONE);
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Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
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for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
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E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
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Reserved.set(*I);
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}
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const R600InstrInfo *RII =
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static_cast<const R600InstrInfo*>(TM.getInstrInfo());
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std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF);
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for (std::vector<unsigned>::iterator I = IndirectRegs.begin(),
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E = IndirectRegs.end();
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I != E; ++I) {
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Reserved.set(*I);
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}
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return Reserved;
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}
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const TargetRegisterClass *
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R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
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switch (rc->getID()) {
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case AMDGPU::GPRF32RegClassID:
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case AMDGPU::GPRI32RegClassID:
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return &AMDGPU::R600_Reg32RegClass;
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default: return rc;
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}
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}
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unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
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return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
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}
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const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
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}
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}
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const RegClassWeight &R600RegisterInfo::getRegClassWeight(
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const TargetRegisterClass *RC) const {
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return RCW;
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}
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