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f60b0de42a
veqv (vector equivalence) vnand vorc I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions. Phabricator review: http://reviews.llvm.org/D7469 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228580 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
976 B
LLVM
28 lines
976 B
LLVM
; Check the miscellaneous logical vector operations added in P8
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;
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
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; Test x eqv y
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define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
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%tmp = xor <4 x i32> %x, %y
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%ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %ret_val
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; CHECK: veqv 2, 2, 3
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}
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; Test x vnand y
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define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
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%tmp = and <4 x i32> %x, %y
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%ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %ret_val
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; CHECK: vnand 2, 2, 3
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}
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; Test x vorc y
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define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
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%tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
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%ret_val = or <4 x i32> %x, %tmp
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ret <4 x i32> %ret_val
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; CHECK: vorc 2, 2, 3
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}
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