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First: refactor out the emission of entries into the .debug_loc section into its own routine. Second: add a new class ByteStreamer that can be used to either emit using an AsmPrinter or hash using DIEHash the series of bytes that would be emitted. Use this in all of the location emission routines for the .debug_loc section. No functional change intended outside of a few additional comments in verbose assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203304 91177308-0d34-0410-b5e6-96231b3b80d8
360 lines
13 KiB
C++
360 lines
13 KiB
C++
//===-- AsmPrinterDwarf.cpp - AsmPrinter Dwarf Support --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Dwarf emissions parts of AsmPrinter.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "ByteStreamer.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSection.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/Dwarf.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Dwarf Emission Helper Routines
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//===----------------------------------------------------------------------===//
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/// EmitSLEB128 - emit the specified signed leb128 value.
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void AsmPrinter::EmitSLEB128(int64_t Value, const char *Desc) const {
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if (isVerbose() && Desc)
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OutStreamer.AddComment(Desc);
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OutStreamer.EmitSLEB128IntValue(Value);
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}
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/// EmitULEB128 - emit the specified signed leb128 value.
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void AsmPrinter::EmitULEB128(uint64_t Value, const char *Desc,
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unsigned PadTo) const {
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if (isVerbose() && Desc)
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OutStreamer.AddComment(Desc);
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OutStreamer.EmitULEB128IntValue(Value, PadTo);
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}
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/// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value.
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void AsmPrinter::EmitCFAByte(unsigned Val) const {
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if (isVerbose()) {
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if (Val >= dwarf::DW_CFA_offset && Val < dwarf::DW_CFA_offset + 64)
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OutStreamer.AddComment("DW_CFA_offset + Reg (" +
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Twine(Val - dwarf::DW_CFA_offset) + ")");
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else
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OutStreamer.AddComment(dwarf::CallFrameString(Val));
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}
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OutStreamer.EmitIntValue(Val, 1);
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}
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static const char *DecodeDWARFEncoding(unsigned Encoding) {
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switch (Encoding) {
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case dwarf::DW_EH_PE_absptr:
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return "absptr";
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case dwarf::DW_EH_PE_omit:
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return "omit";
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case dwarf::DW_EH_PE_pcrel:
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return "pcrel";
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case dwarf::DW_EH_PE_udata4:
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return "udata4";
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case dwarf::DW_EH_PE_udata8:
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return "udata8";
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case dwarf::DW_EH_PE_sdata4:
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return "sdata4";
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case dwarf::DW_EH_PE_sdata8:
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return "sdata8";
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case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4:
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return "pcrel udata4";
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case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4:
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return "pcrel sdata4";
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case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8:
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return "pcrel udata8";
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case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8:
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return "pcrel sdata8";
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case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4
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:
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return "indirect pcrel udata4";
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case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
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:
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return "indirect pcrel sdata4";
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case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8
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:
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return "indirect pcrel udata8";
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case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8
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:
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return "indirect pcrel sdata8";
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}
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return "<unknown encoding>";
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}
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/// EmitEncodingByte - Emit a .byte 42 directive that corresponds to an
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/// encoding. If verbose assembly output is enabled, we output comments
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/// describing the encoding. Desc is an optional string saying what the
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/// encoding is specifying (e.g. "LSDA").
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void AsmPrinter::EmitEncodingByte(unsigned Val, const char *Desc) const {
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if (isVerbose()) {
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if (Desc)
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OutStreamer.AddComment(Twine(Desc) + " Encoding = " +
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Twine(DecodeDWARFEncoding(Val)));
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else
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OutStreamer.AddComment(Twine("Encoding = ") + DecodeDWARFEncoding(Val));
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}
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OutStreamer.EmitIntValue(Val, 1);
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}
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/// GetSizeOfEncodedValue - Return the size of the encoding in bytes.
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unsigned AsmPrinter::GetSizeOfEncodedValue(unsigned Encoding) const {
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if (Encoding == dwarf::DW_EH_PE_omit)
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return 0;
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switch (Encoding & 0x07) {
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default:
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llvm_unreachable("Invalid encoded value.");
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case dwarf::DW_EH_PE_absptr:
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return TM.getDataLayout()->getPointerSize();
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case dwarf::DW_EH_PE_udata2:
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return 2;
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case dwarf::DW_EH_PE_udata4:
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return 4;
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case dwarf::DW_EH_PE_udata8:
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return 8;
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}
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}
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void AsmPrinter::EmitTTypeReference(const GlobalValue *GV,
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unsigned Encoding) const {
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if (GV) {
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const TargetLoweringObjectFile &TLOF = getObjFileLowering();
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const MCExpr *Exp =
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TLOF.getTTypeGlobalReference(GV, Encoding, *Mang, TM, MMI, OutStreamer);
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OutStreamer.EmitValue(Exp, GetSizeOfEncodedValue(Encoding));
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} else
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OutStreamer.EmitIntValue(0, GetSizeOfEncodedValue(Encoding));
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}
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/// EmitSectionOffset - Emit the 4-byte offset of Label from the start of its
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/// section. This can be done with a special directive if the target supports
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/// it (e.g. cygwin) or by emitting it as an offset from a label at the start
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/// of the section.
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///
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/// SectionLabel is a temporary label emitted at the start of the section that
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/// Label lives in.
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void AsmPrinter::EmitSectionOffset(const MCSymbol *Label,
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const MCSymbol *SectionLabel) const {
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// On COFF targets, we have to emit the special .secrel32 directive.
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if (MAI->needsDwarfSectionOffsetDirective()) {
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OutStreamer.EmitCOFFSecRel32(Label);
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return;
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}
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// Get the section that we're referring to, based on SectionLabel.
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const MCSection &Section = SectionLabel->getSection();
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// If Label has already been emitted, verify that it is in the same section as
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// section label for sanity.
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assert((!Label->isInSection() || &Label->getSection() == &Section) &&
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"Section offset using wrong section base for label");
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// If the section in question will end up with an address of 0 anyway, we can
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// just emit an absolute reference to save a relocation.
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if (Section.isBaseAddressKnownZero()) {
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OutStreamer.EmitSymbolValue(Label, 4);
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return;
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}
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// Otherwise, emit it as a label difference from the start of the section.
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EmitLabelDifference(Label, SectionLabel, 4);
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}
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/// Emit a dwarf register operation.
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static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) {
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assert(Reg >= 0);
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if (Reg < 32) {
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Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
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dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
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} else {
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Streamer.EmitInt8(dwarf::DW_OP_regx, "DW_OP_regx");
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Streamer.EmitULEB128(Reg, Twine(Reg));
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}
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}
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/// Emit an (double-)indirect dwarf register operation.
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static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset,
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bool Deref) {
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assert(Reg >= 0);
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if (Reg < 32) {
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Streamer.EmitInt8(dwarf::DW_OP_breg0 + Reg,
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dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
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} else {
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Streamer.EmitInt8(dwarf::DW_OP_bregx, "DW_OP_bregx");
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Streamer.EmitULEB128(Reg, Twine(Reg));
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}
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Streamer.EmitSLEB128(Offset);
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if (Deref)
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Streamer.EmitInt8(dwarf::DW_OP_deref, "DW_OP_deref");
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}
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/// Emit a dwarf register operation for describing
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/// - a small value occupying only part of a register or
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/// - a small register representing only part of a value.
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static void emitDwarfOpPiece(ByteStreamer &Streamer, unsigned Size,
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unsigned Offset) {
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assert(Size > 0);
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if (Offset > 0) {
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Streamer.EmitInt8(dwarf::DW_OP_bit_piece, "DW_OP_bit_piece");
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Streamer.EmitULEB128(Size, Twine(Size));
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Streamer.EmitULEB128(Offset, Twine(Offset));
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} else {
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Streamer.EmitInt8(dwarf::DW_OP_piece, "DW_OP_piece");
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unsigned ByteSize = Size / 8; // Assuming 8 bits per byte.
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Streamer.EmitULEB128(ByteSize, Twine(ByteSize));
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}
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}
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/// Some targets do not provide a DWARF register number for every
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/// register. This function attempts to emit a dwarf register by
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/// emitting a piece of a super-register or by piecing together
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/// multiple subregisters that alias the register.
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static void EmitDwarfRegOpPiece(ByteStreamer &Streamer, const AsmPrinter &AP,
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const MachineLocation &MLoc) {
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assert(!MLoc.isIndirect());
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const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
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int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
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// Walk up the super-register chain until we find a valid number.
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// For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
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for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
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Reg = TRI->getDwarfRegNum(*SR, false);
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if (Reg >= 0) {
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unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
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unsigned Size = TRI->getSubRegIdxSize(Idx);
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unsigned Offset = TRI->getSubRegIdxOffset(Idx);
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AP.OutStreamer.AddComment("super-register");
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emitDwarfRegOp(Streamer, Reg);
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emitDwarfOpPiece(Streamer, Size, Offset);
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return;
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}
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}
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// Otherwise, attempt to find a covering set of sub-register numbers.
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// For example, Q0 on ARM is a composition of D0+D1.
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//
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// Keep track of the current position so we can emit the more
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// efficient DW_OP_piece.
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unsigned CurPos = 0;
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// The size of the register in bits, assuming 8 bits per byte.
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unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8;
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// Keep track of the bits in the register we already emitted, so we
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// can avoid emitting redundant aliasing subregs.
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SmallBitVector Coverage(RegSize, false);
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for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
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unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR);
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unsigned Size = TRI->getSubRegIdxSize(Idx);
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unsigned Offset = TRI->getSubRegIdxOffset(Idx);
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Reg = TRI->getDwarfRegNum(*SR, false);
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// Intersection between the bits we already emitted and the bits
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// covered by this subregister.
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SmallBitVector Intersection(RegSize, false);
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Intersection.set(Offset, Offset + Size);
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Intersection ^= Coverage;
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// If this sub-register has a DWARF number and we haven't covered
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// its range, emit a DWARF piece for it.
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if (Reg >= 0 && Intersection.any()) {
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AP.OutStreamer.AddComment("sub-register");
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emitDwarfRegOp(Streamer, Reg);
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emitDwarfOpPiece(Streamer, Size, Offset == CurPos ? 0 : Offset);
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CurPos = Offset + Size;
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// Mark it as emitted.
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Coverage.set(Offset, Offset + Size);
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}
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}
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if (CurPos == 0) {
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// FIXME: We have no reasonable way of handling errors in here.
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Streamer.EmitInt8(dwarf::DW_OP_nop,
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"nop (could not find a dwarf register number)");
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}
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}
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/// EmitDwarfRegOp - Emit dwarf register operation.
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void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer,
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const MachineLocation &MLoc,
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bool Indirect) const {
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
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if (Reg < 0) {
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// We assume that pointers are always in an addressable register.
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if (Indirect || MLoc.isIndirect()) {
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// FIXME: We have no reasonable way of handling errors in here. The
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// caller might be in the middle of a dwarf expression. We should
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// probably assert that Reg >= 0 once debug info generation is more
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// mature.
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Streamer.EmitInt8(dwarf::DW_OP_nop,
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"nop (invalid dwarf register number for indirect loc)");
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return;
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}
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// Attempt to find a valid super- or sub-register.
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if (!Indirect && !MLoc.isIndirect())
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return EmitDwarfRegOpPiece(Streamer, *this, MLoc);
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}
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if (MLoc.isIndirect())
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emitDwarfRegOpIndirect(Streamer, Reg, MLoc.getOffset(), Indirect);
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else if (Indirect)
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emitDwarfRegOpIndirect(Streamer, Reg, 0, false);
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else
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emitDwarfRegOp(Streamer, Reg);
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}
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//===----------------------------------------------------------------------===//
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// Dwarf Lowering Routines
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//===----------------------------------------------------------------------===//
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void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
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switch (Inst.getOperation()) {
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default:
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llvm_unreachable("Unexpected instruction");
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case MCCFIInstruction::OpDefCfaOffset:
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OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset());
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break;
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case MCCFIInstruction::OpDefCfa:
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OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset());
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break;
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case MCCFIInstruction::OpDefCfaRegister:
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OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister());
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break;
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case MCCFIInstruction::OpOffset:
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OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset());
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break;
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case MCCFIInstruction::OpRegister:
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OutStreamer.EmitCFIRegister(Inst.getRegister(), Inst.getRegister2());
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break;
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case MCCFIInstruction::OpWindowSave:
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OutStreamer.EmitCFIWindowSave();
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break;
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}
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}
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