llvm-6502/test/CodeGen
Gerolf Hoflehner e4fa341dde MachineCombiner Pass for selecting faster instruction sequence on AArch64
Re-commit of r214832,r21469 with a work-around that
avoids the previous problem with gcc build compilers

The work-around is to use SmallVector instead of ArrayRef
of basic blocks in preservesResourceLen()/MachineCombiner.cpp



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215151 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-07 21:40:58 +00:00
..
AArch64 MachineCombiner Pass for selecting faster instruction sequence on AArch64 2014-08-07 21:40:58 +00:00
ARM [Branch probability] Recompute branch weights of tail-merged basic blocks. 2014-08-07 19:30:13 +00:00
CPP
Generic
Hexagon DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range. 2014-08-06 00:21:25 +00:00
Inputs
Mips
MSP430
NVPTX
PowerPC [PowerPC] Swap arguments and adjust shift count for vsldoi on little endian 2014-08-05 20:47:25 +00:00
R600 R600: Cleanup fadd and fsub tests 2014-08-06 20:27:55 +00:00
SPARC
SystemZ
Thumb
Thumb2 ARM: do not generate BLX instructions on Cortex-M CPUs. 2014-08-06 11:13:14 +00:00
X86 [x86] Fix another miscompile found through fuzz testing the new vector 2014-08-07 10:37:35 +00:00
XCore