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https://github.com/c64scene-ar/llvm-6502.git
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Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159027 91177308-0d34-0410-b5e6-96231b3b80d8
168 lines
5.9 KiB
C++
168 lines
5.9 KiB
C++
//=- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This class implements a deterministic finite automaton (DFA) based
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// packetizing mechanism for VLIW architectures. It provides APIs to
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// determine whether there exists a legal mapping of instructions to
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// functional unit assignments in a packet. The DFA is auto-generated from
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// the target's Schedule.td file.
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//
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// A DFA consists of 3 major elements: states, inputs, and transitions. For
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// the packetizing mechanism, the input is the set of instruction classes for
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// a target. The state models all possible combinations of functional unit
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// consumption for a given set of instructions in a packet. A transition
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// models the addition of an instruction to a packet. In the DFA constructed
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// by this class, if an instruction can be added to a packet, then a valid
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// transition exists from the corresponding state. Invalid transitions
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// indicate that the instruction cannot be added to the current packet.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_DFAPACKETIZER_H
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#define LLVM_CODEGEN_DFAPACKETIZER_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/ADT/DenseMap.h"
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#include <map>
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namespace llvm {
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class MCInstrDesc;
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class MachineInstr;
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class MachineLoopInfo;
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class MachineDominatorTree;
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class InstrItineraryData;
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class DefaultVLIWScheduler;
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class SUnit;
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class DFAPacketizer {
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private:
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typedef std::pair<unsigned, unsigned> UnsignPair;
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const InstrItineraryData *InstrItins;
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int CurrentState;
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const int (*DFAStateInputTable)[2];
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const unsigned *DFAStateEntryTable;
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// CachedTable is a map from <FromState, Input> to ToState.
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DenseMap<UnsignPair, unsigned> CachedTable;
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// ReadTable - Read the DFA transition table and update CachedTable.
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void ReadTable(unsigned int state);
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public:
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DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
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const unsigned *SET);
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// Reset the current state to make all resources available.
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void clearResources() {
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CurrentState = 0;
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}
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state.
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bool canReserveResources(const llvm::MCInstrDesc *MID);
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change.
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void reserveResources(const llvm::MCInstrDesc *MID);
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// canReserveResources - Check if the resources occupied by a machine
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// instruction are available in the current state.
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bool canReserveResources(llvm::MachineInstr *MI);
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// reserveResources - Reserve the resources occupied by a machine
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// instruction and change the current state to reflect that change.
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void reserveResources(llvm::MachineInstr *MI);
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const InstrItineraryData *getInstrItins() const { return InstrItins; }
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};
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// VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The
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// packetizer works on machine basic blocks. For each instruction I in BB, the
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// packetizer consults the DFA to see if machine resources are available to
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// execute I. If so, the packetizer checks if I depends on any instruction J in
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// the current packet. If no dependency is found, I is added to current packet
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// and machine resource is marked as taken. If any dependency is found, a target
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// API call is made to prune the dependence.
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class VLIWPacketizerList {
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protected:
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const TargetMachine &TM;
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const MachineFunction &MF;
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const TargetInstrInfo *TII;
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// The VLIW Scheduler.
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DefaultVLIWScheduler *VLIWScheduler;
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// Vector of instructions assigned to the current packet.
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std::vector<MachineInstr*> CurrentPacketMIs;
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// DFA resource tracker.
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DFAPacketizer *ResourceTracker;
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// Generate MI -> SU map.
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std::map<MachineInstr*, SUnit*> MIToSUnit;
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public:
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VLIWPacketizerList(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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bool IsPostRA);
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virtual ~VLIWPacketizerList();
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// PacketizeMIs - Implement this API in the backend to bundle instructions.
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void PacketizeMIs(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator BeginItr,
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MachineBasicBlock::iterator EndItr);
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// getResourceTracker - return ResourceTracker
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DFAPacketizer *getResourceTracker() {return ResourceTracker;}
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// addToPacket - Add MI to the current packet.
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virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
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MachineBasicBlock::iterator MII = MI;
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CurrentPacketMIs.push_back(MI);
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ResourceTracker->reserveResources(MI);
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return MII;
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}
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// endPacket - End the current packet.
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void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
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// initPacketizerState - perform initialization before packetizing
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// an instruction. This function is supposed to be overrided by
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// the target dependent packetizer.
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virtual void initPacketizerState(void) { return; }
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// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
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virtual bool ignorePseudoInstruction(MachineInstr *I,
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MachineBasicBlock *MBB) {
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return false;
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}
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// isSoloInstruction - return true if instruction MI can not be packetized
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// with any other instruction, which means that MI itself is a packet.
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virtual bool isSoloInstruction(MachineInstr *MI) {
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return true;
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}
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// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
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// together.
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virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
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return false;
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}
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// isLegalToPruneDependencies - Is it legal to prune dependece between SUI
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// and SUJ.
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virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
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return false;
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}
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};
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}
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#endif
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