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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165950 91177308-0d34-0410-b5e6-96231b3b80d8
329 lines
10 KiB
C++
329 lines
10 KiB
C++
//==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides a MachineSchedRegistry for registering alternative machine
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// schedulers. A Target may provide an alternative scheduler implementation by
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// implementing the following boilerplate:
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//
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// static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
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// return new CustomMachineScheduler(C);
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// }
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// static MachineSchedRegistry
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// SchedCustomRegistry("custom", "Run my target's custom scheduler",
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// createCustomMachineSched);
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//
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// Inside <Target>PassConfig:
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// enablePass(&MachineSchedulerID);
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// MachineSchedRegistry::setDefault(createCustomMachineSched);
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//
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//===----------------------------------------------------------------------===//
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#ifndef MACHINESCHEDULER_H
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#define MACHINESCHEDULER_H
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#include "llvm/CodeGen/MachinePassRegistry.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/Target/TargetInstrInfo.h"
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namespace llvm {
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extern cl::opt<bool> ForceTopDown;
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extern cl::opt<bool> ForceBottomUp;
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class AliasAnalysis;
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class LiveIntervals;
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class MachineDominatorTree;
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class MachineLoopInfo;
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class RegisterClassInfo;
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class ScheduleDAGInstrs;
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/// MachineSchedContext provides enough context from the MachineScheduler pass
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/// for the target to instantiate a scheduler.
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struct MachineSchedContext {
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MachineFunction *MF;
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const MachineLoopInfo *MLI;
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const MachineDominatorTree *MDT;
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const TargetPassConfig *PassConfig;
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AliasAnalysis *AA;
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LiveIntervals *LIS;
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RegisterClassInfo *RegClassInfo;
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MachineSchedContext();
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virtual ~MachineSchedContext();
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};
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/// MachineSchedRegistry provides a selection of available machine instruction
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/// schedulers.
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class MachineSchedRegistry : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
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// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
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typedef ScheduleDAGCtor FunctionPassCtor;
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static MachinePassRegistry Registry;
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MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
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: MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
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Registry.Add(this);
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}
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~MachineSchedRegistry() { Registry.Remove(this); }
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// Accessors.
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//
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MachineSchedRegistry *getNext() const {
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return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
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}
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static MachineSchedRegistry *getList() {
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return (MachineSchedRegistry *)Registry.getList();
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}
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static ScheduleDAGCtor getDefault() {
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return (ScheduleDAGCtor)Registry.getDefault();
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}
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static void setDefault(ScheduleDAGCtor C) {
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Registry.setDefault((MachinePassCtor)C);
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}
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static void setDefault(StringRef Name) {
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Registry.setDefault(Name);
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}
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static void setListener(MachinePassRegistryListener *L) {
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Registry.setListener(L);
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}
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};
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class ScheduleDAGMI;
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/// MachineSchedStrategy - Interface to the scheduling algorithm used by
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/// ScheduleDAGMI.
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class MachineSchedStrategy {
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public:
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virtual ~MachineSchedStrategy() {}
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/// Initialize the strategy after building the DAG for a new region.
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virtual void initialize(ScheduleDAGMI *DAG) = 0;
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/// Notify this strategy that all roots have been released (including those
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/// that depend on EntrySU or ExitSU).
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virtual void registerRoots() {}
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/// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
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/// schedule the node at the top of the unscheduled region. Otherwise it will
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/// be scheduled at the bottom.
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virtual SUnit *pickNode(bool &IsTopNode) = 0;
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/// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
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/// instruction and updated scheduled/remaining flags in the DAG nodes.
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virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
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/// When all predecessor dependencies have been resolved, free this node for
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/// top-down scheduling.
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virtual void releaseTopNode(SUnit *SU) = 0;
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/// When all successor dependencies have been resolved, free this node for
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/// bottom-up scheduling.
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virtual void releaseBottomNode(SUnit *SU) = 0;
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};
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/// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
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/// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
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/// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
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///
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/// This is a convenience class that may be used by implementations of
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/// MachineSchedStrategy.
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class ReadyQueue {
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unsigned ID;
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std::string Name;
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std::vector<SUnit*> Queue;
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public:
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ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
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unsigned getID() const { return ID; }
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StringRef getName() const { return Name; }
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// SU is in this queue if it's NodeQueueID is a superset of this ID.
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bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
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bool empty() const { return Queue.empty(); }
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unsigned size() const { return Queue.size(); }
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typedef std::vector<SUnit*>::iterator iterator;
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iterator begin() { return Queue.begin(); }
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iterator end() { return Queue.end(); }
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iterator find(SUnit *SU) {
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return std::find(Queue.begin(), Queue.end(), SU);
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}
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void push(SUnit *SU) {
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Queue.push_back(SU);
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SU->NodeQueueId |= ID;
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}
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void remove(iterator I) {
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(*I)->NodeQueueId &= ~ID;
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*I = Queue.back();
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Queue.pop_back();
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}
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#ifndef NDEBUG
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void dump();
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#endif
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};
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/// Mutate the DAG as a postpass after normal DAG building.
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class ScheduleDAGMutation {
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public:
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virtual ~ScheduleDAGMutation() {}
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virtual void apply(ScheduleDAGMI *DAG) = 0;
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};
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/// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
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/// machine instructions while updating LiveIntervals and tracking regpressure.
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class ScheduleDAGMI : public ScheduleDAGInstrs {
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protected:
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AliasAnalysis *AA;
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RegisterClassInfo *RegClassInfo;
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MachineSchedStrategy *SchedImpl;
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/// Ordered list of DAG postprocessing steps.
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std::vector<ScheduleDAGMutation*> Mutations;
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MachineBasicBlock::iterator LiveRegionEnd;
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/// Register pressure in this region computed by buildSchedGraph.
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IntervalPressure RegPressure;
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RegPressureTracker RPTracker;
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/// List of pressure sets that exceed the target's pressure limit before
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/// scheduling, listed in increasing set ID order. Each pressure set is paired
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/// with its max pressure in the currently scheduled regions.
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std::vector<PressureElement> RegionCriticalPSets;
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/// The top of the unscheduled zone.
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MachineBasicBlock::iterator CurrentTop;
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IntervalPressure TopPressure;
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RegPressureTracker TopRPTracker;
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/// The bottom of the unscheduled zone.
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MachineBasicBlock::iterator CurrentBottom;
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IntervalPressure BotPressure;
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RegPressureTracker BotRPTracker;
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#ifndef NDEBUG
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/// The number of instructions scheduled so far. Used to cut off the
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/// scheduler at the point determined by misched-cutoff.
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unsigned NumInstrsScheduled;
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#endif
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public:
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ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
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ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
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AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
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RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
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CurrentBottom(), BotRPTracker(BotPressure) {
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#ifndef NDEBUG
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NumInstrsScheduled = 0;
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#endif
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}
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virtual ~ScheduleDAGMI() {
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delete SchedImpl;
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}
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/// Add a postprocessing step to the DAG builder.
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/// Mutations are applied in the order that they are added after normal DAG
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/// building and before MachineSchedStrategy initialization.
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void addMutation(ScheduleDAGMutation *Mutation) {
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Mutations.push_back(Mutation);
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}
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MachineBasicBlock::iterator top() const { return CurrentTop; }
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MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
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/// Implement the ScheduleDAGInstrs interface for handling the next scheduling
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/// region. This covers all instructions in a block, while schedule() may only
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/// cover a subset.
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void enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned endcount);
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/// Implement ScheduleDAGInstrs interface for scheduling a sequence of
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/// reorderable instructions.
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virtual void schedule();
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/// Get current register pressure for the top scheduled instructions.
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const IntervalPressure &getTopPressure() const { return TopPressure; }
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const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
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/// Get current register pressure for the bottom scheduled instructions.
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const IntervalPressure &getBotPressure() const { return BotPressure; }
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const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
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/// Get register pressure for the entire scheduling region before scheduling.
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const IntervalPressure &getRegPressure() const { return RegPressure; }
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const std::vector<PressureElement> &getRegionCriticalPSets() const {
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return RegionCriticalPSets;
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}
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protected:
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// Top-Level entry points for the schedule() driver...
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/// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking
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/// enabled. This sets up three trackers. RPTracker will cover the entire DAG
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/// region, TopTracker and BottomTracker will be initialized to the top and
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/// bottom of the DAG region without covereing any unscheduled instruction.
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void buildDAGWithRegPressure();
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/// Apply each ScheduleDAGMutation step in order. This allows different
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/// instances of ScheduleDAGMI to perform custom DAG postprocessing.
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void postprocessDAG();
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/// Identify DAG roots and setup scheduler queues.
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void initQueues();
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/// Move an instruction and update register pressure.
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void scheduleMI(SUnit *SU, bool IsTopNode);
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/// Update scheduler DAG and queues after scheduling an instruction.
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void updateQueues(SUnit *SU, bool IsTopNode);
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/// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
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void placeDebugValues();
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// Lesser helpers...
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void initRegPressure();
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void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
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void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
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bool checkSchedLimit();
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void releaseRoots();
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSuccessors(SUnit *SU);
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void releasePred(SUnit *SU, SDep *PredEdge);
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void releasePredecessors(SUnit *SU);
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};
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} // namespace llvm
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#endif
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