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https://github.com/c64scene-ar/llvm-6502.git
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4a971705bc
It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
3.2 KiB
C++
99 lines
3.2 KiB
C++
//===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Hexagon specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonMCTargetDesc.h"
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#include "HexagonMCAsmInfo.h"
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#include "InstPrinter/HexagonInstPrinter.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_MC_DESC
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#include "HexagonGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "HexagonGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "HexagonGenRegisterInfo.inc"
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using namespace llvm;
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static MCInstrInfo *createHexagonMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitHexagonMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitHexagonMCRegisterInfo(X, Hexagon::R0);
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return X;
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}
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static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT,
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StringRef CPU,
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StringRef FS) {
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
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return X;
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}
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static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
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StringRef TT) {
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MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
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// VirtualFP = (R30 + #0).
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
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0, Hexagon::R30, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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// For the time being, use static relocations, since there's really no
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// support for PIC yet.
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X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
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return X;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeHexagonTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget,
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createHexagonMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget, createHexagonMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,
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createHexagonMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget,
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createHexagonMCSubtargetInfo);
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}
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