llvm-6502/test/MC/PowerPC/ppc64-errors.s
Ulrich Weigand 5e220753ff [PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.

The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux.  The supported syntax is
intended to be compatible with the GNU assembler.

The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.

Instruction operands will be checked for validity and errors
generated.  (Error handling in general could still be improved.)

The patch adds a number of test cases to verify instruction
and operand encodings.  The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector. 
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.

A number of follow-on check-ins will add extra features.  When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 19:49:39 +00:00

81 lines
1.9 KiB
ArmAsm

# RUN: not llvm-mc -triple powerpc64-unknown-unknown < %s 2> %t
# RUN: FileCheck < %t %s
# Register operands
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: add 32, 32, 32
add 32, 32, 32
# CHECK: error: invalid register name
# CHECK-NEXT: add %r32, %r32, %r32
add %r32, %r32, %r32
# Signed 16-bit immediate operands
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: addi 1, 0, -32769
addi 1, 0, -32769
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: addi 1, 0, 32768
addi 1, 0, 32768
# Unsigned 16-bit immediate operands
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: ori 1, 2, -1
ori 1, 2, -1
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: ori 1, 2, 65536
ori 1, 2, 65536
# D-Form memory operands
# CHECK: error: invalid register number
# CHECK-NEXT: lwz 1, 0(32)
lwz 1, 0(32)
# CHECK: error: invalid register name
# CHECK-NEXT: lwz 1, 0(%r32)
lwz 1, 0(%r32)
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: lwz 1, -32769(2)
lwz 1, -32769(2)
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: lwz 1, 32768(2)
lwz 1, 32768(2)
# CHECK: error: invalid register number
# CHECK-NEXT: ld 1, 0(32)
ld 1, 0(32)
# CHECK: error: invalid register name
# CHECK-NEXT: ld 1, 0(%r32)
ld 1, 0(%r32)
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: ld 1, 1(2)
ld 1, 1(2)
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: ld 1, 2(2)
ld 1, 2(2)
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: ld 1, 3(2)
ld 1, 3(2)
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: ld 1, -32772(2)
ld 1, -32772(2)
# CHECK: error: invalid operand for instruction
# CHECK-NEXT: ld 1, 32768(2)
ld 1, 32768(2)