mirror of
https://github.com/c64scene-ar/llvm-6502.git
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5e220753ff
This adds assembler parser support to the PowerPC back end. The parser will run for any powerpc-*-* and powerpc64-*-* triples, but was tested only on 64-bit Linux. The supported syntax is intended to be compatible with the GNU assembler. The parser does not yet support all PowerPC instructions, but it does support anything that is generated by LLVM itself. There is no support for testing restricted instruction sets yet, i.e. the parser will always accept any instructions it knows, no matter what feature flags are given. Instruction operands will be checked for validity and errors generated. (Error handling in general could still be improved.) The patch adds a number of test cases to verify instruction and operand encodings. The tests currently cover all instructions from the following PowerPC ISA v2.06 Book I facilities: Branch, Fixed-point, Floating-Point, and Vector. Note that a number of these instructions are not yet supported by the back end; they are marked with FIXME. A number of follow-on check-ins will add extra features. When they are all included, LLVM passes all tests (including bootstrap) when using clang -cc1as as the system assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
88 lines
2.6 KiB
ArmAsm
88 lines
2.6 KiB
ArmAsm
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# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
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# Register operands
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# CHECK: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14]
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add 1, 2, 3
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# CHECK: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14]
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add %r1, %r2, %r3
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# CHECK: add 0, 0, 0 # encoding: [0x7c,0x00,0x02,0x14]
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add 0, 0, 0
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# CHECK: add 31, 31, 31 # encoding: [0x7f,0xff,0xfa,0x14]
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add 31, 31, 31
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# CHECK: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00]
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addi 1, 0, 0
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# CHECK: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00]
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addi 1, %r0, 0
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# Signed 16-bit immediate operands
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# CHECK: addi 1, 2, 0 # encoding: [0x38,0x22,0x00,0x00]
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addi 1, 2, 0
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# CHECK: addi 1, 0, -32768 # encoding: [0x38,0x20,0x80,0x00]
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addi 1, 0, -32768
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# CHECK: addi 1, 0, 32767 # encoding: [0x38,0x20,0x7f,0xff]
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addi 1, 0, 32767
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# Unsigned 16-bit immediate operands
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# CHECK: ori 1, 2, 0 # encoding: [0x60,0x41,0x00,0x00]
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ori 1, 2, 0
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# CHECK: ori 1, 2, 65535 # encoding: [0x60,0x41,0xff,0xff]
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ori 1, 2, 65535
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# D-Form memory operands
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# CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00]
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lwz 1, 0(0)
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# CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00]
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lwz 1, 0(%r0)
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# CHECK: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00]
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lwz 1, 0(31)
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# CHECK: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00]
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lwz 1, 0(%r31)
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# CHECK: lwz 1, -32768(2) # encoding: [0x80,0x22,0x80,0x00]
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lwz 1, -32768(2)
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# CHECK: lwz 1, 32767(2) # encoding: [0x80,0x22,0x7f,0xff]
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lwz 1, 32767(2)
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# CHECK: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00]
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ld 1, 0(0)
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# CHECK: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00]
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ld 1, 0(%r0)
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# CHECK: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00]
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ld 1, 0(31)
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# CHECK: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00]
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ld 1, 0(%r31)
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# CHECK: ld 1, -32768(2) # encoding: [0xe8,0x22,0x80,0x00]
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ld 1, -32768(2)
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# CHECK: ld 1, 32764(2) # encoding: [0xe8,0x22,0x7f,0xfc]
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ld 1, 32764(2)
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# CHECK: ld 1, 4(2) # encoding: [0xe8,0x22,0x00,0x04]
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ld 1, 4(2)
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# CHECK: ld 1, -4(2) # encoding: [0xe8,0x22,0xff,0xfc]
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ld 1, -4(2)
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