mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
9d172d5ee7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89723 91177308-0d34-0410-b5e6-96231b3b80d8
460 lines
17 KiB
TableGen
460 lines
17 KiB
TableGen
//===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM VFP instruction set.
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//
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//===----------------------------------------------------------------------===//
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def SDT_FTOI :
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDT_ITOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SDT_CMPFP0 :
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SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def SDT_VMOVDRR :
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SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
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def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
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def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
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def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
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def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
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def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
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def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
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//===----------------------------------------------------------------------===//
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// Operand Definitions.
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//
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def vfp_f32imm : Operand<f32>,
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PatLeaf<(f32 fpimm), [{
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return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
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}]> {
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let PrintMethod = "printVFPf32ImmOperand";
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}
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def vfp_f64imm : Operand<f64>,
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PatLeaf<(f64 fpimm), [{
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return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
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}]> {
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let PrintMethod = "printVFPf64ImmOperand";
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}
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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//
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let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
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def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
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IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
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[(set DPR:$dst, (load addrmode5:$addr))]>;
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def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
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IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
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[(set SPR:$dst, (load addrmode5:$addr))]>;
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} // canFoldAsLoad
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def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
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IIC_fpStore64, "vstr", ".64\t$src, $addr",
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[(store DPR:$src, addrmode5:$addr)]>;
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def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
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IIC_fpStore32, "vstr", ".32\t$src, $addr",
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[(store SPR:$src, addrmode5:$addr)]>;
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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//
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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def VLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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variable_ops), IIC_fpLoadm,
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"vldm${addr:submode}${p}\t${addr:base}, $wb",
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[]> {
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let Inst{20} = 1;
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}
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def VLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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variable_ops), IIC_fpLoadm,
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"vldm${addr:submode}${p}\t${addr:base}, $wb",
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[]> {
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let Inst{20} = 1;
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}
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} // mayLoad, hasExtraDefRegAllocReq
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
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def VSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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variable_ops), IIC_fpStorem,
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"vstm${addr:submode}${p}\t${addr:base}, $wb",
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[]> {
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let Inst{20} = 0;
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}
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def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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variable_ops), IIC_fpStorem,
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"vstm${addr:submode}${p}\t${addr:base}, $wb",
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[]> {
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let Inst{20} = 0;
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}
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} // mayStore, hasExtraSrcRegAllocReq
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// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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//===----------------------------------------------------------------------===//
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// FP Binary Operations.
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//
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def VADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
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def VADDS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpALU32, "vadd", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
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// These are encoded as unary instructions.
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let Defs = [FPSCR] in {
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def VCMPED : ADuI<0b11101011, 0b0100, 0b1100, (outs), (ins DPR:$a, DPR:$b),
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IIC_fpCMP64, "vcmpe", ".f64\t$a, $b",
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[(arm_cmpfp DPR:$a, DPR:$b)]>;
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def VCMPES : ASuI<0b11101011, 0b0100, 0b1100, (outs), (ins SPR:$a, SPR:$b),
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IIC_fpCMP32, "vcmpe", ".f32\t$a, $b",
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[(arm_cmpfp SPR:$a, SPR:$b)]>;
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}
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def VDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
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def VDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpDIV32, "vdiv", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
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def VMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpMUL64, "vmul", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
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def VMULS : ASbIn<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpMUL32, "vmul", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
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def VNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpMUL64, "vnmul", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
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let Inst{6} = 1;
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}
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def VNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpMUL32, "vnmul", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
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let Inst{6} = 1;
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}
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// Match reassociated forms only if not sign dependent rounding.
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def : Pat<(fmul (fneg DPR:$a), DPR:$b),
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(VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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def : Pat<(fmul (fneg SPR:$a), SPR:$b),
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(VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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def VSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpALU64, "vsub", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]> {
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let Inst{6} = 1;
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}
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def VSUBS : ASbIn<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpALU32, "vsub", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fsub SPR:$a, SPR:$b))]> {
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let Inst{6} = 1;
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}
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//===----------------------------------------------------------------------===//
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// FP Unary Operations.
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//
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def VABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
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IIC_fpUNA64, "vabs", ".f64\t$dst, $a",
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[(set DPR:$dst, (fabs DPR:$a))]>;
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def VABSS : ASuIn<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
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IIC_fpUNA32, "vabs", ".f32\t$dst, $a",
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[(set SPR:$dst, (fabs SPR:$a))]>;
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let Defs = [FPSCR] in {
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def VCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
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IIC_fpCMP64, "vcmpe", ".f64\t$a, #0",
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[(arm_cmpfp0 DPR:$a)]>;
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def VCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
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IIC_fpCMP32, "vcmpe", ".f32\t$a, #0",
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[(arm_cmpfp0 SPR:$a)]>;
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}
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def VCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
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IIC_fpCVTDS, "vcvt", ".f64.f32\t$dst, $a",
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[(set DPR:$dst, (fextend SPR:$a))]>;
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// Special case encoding: bits 11-8 is 0b1011.
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def VCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
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IIC_fpCVTSD, "vcvt", ".f32.f64\t$dst, $a",
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[(set SPR:$dst, (fround DPR:$a))]> {
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let Inst{27-23} = 0b11101;
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let Inst{21-16} = 0b110111;
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let Inst{11-8} = 0b1011;
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let Inst{7-4} = 0b1100;
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}
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let neverHasSideEffects = 1 in {
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def VMOVD: ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
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IIC_fpUNA64, "vmov", ".f64\t$dst, $a", []>;
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def VMOVS: ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
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IIC_fpUNA32, "vmov", ".f32\t$dst, $a", []>;
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} // neverHasSideEffects
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def VNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
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IIC_fpUNA64, "vneg", ".f64\t$dst, $a",
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[(set DPR:$dst, (fneg DPR:$a))]>;
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def VNEGS : ASuIn<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
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IIC_fpUNA32, "vneg", ".f32\t$dst, $a",
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[(set SPR:$dst, (fneg SPR:$a))]>;
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def VSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
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IIC_fpSQRT64, "vsqrt", ".f64\t$dst, $a",
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[(set DPR:$dst, (fsqrt DPR:$a))]>;
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def VSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
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IIC_fpSQRT32, "vsqrt", ".f32\t$dst, $a",
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[(set SPR:$dst, (fsqrt SPR:$a))]>;
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//===----------------------------------------------------------------------===//
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// FP <-> GPR Copies. Int <-> FP Conversions.
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//
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def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
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IIC_VMOVSI, "vmov", "\t$dst, $src",
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[(set GPR:$dst, (bitconvert SPR:$src))]>;
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def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
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IIC_VMOVIS, "vmov", "\t$dst, $src",
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[(set SPR:$dst, (bitconvert GPR:$src))]>;
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def VMOVRRD : AVConv3I<0b11000101, 0b1011,
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(outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
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IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src",
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[/* FIXME: Can't write pattern for multiple result instr*/]>;
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// FMDHR: GPR -> SPR
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// FMDLR: GPR -> SPR
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def VMOVDRR : AVConv5I<0b11000100, 0b1011,
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(outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
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IIC_VMOVID, "vmov", "\t$dst, $src1, $src2",
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[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
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// FMRDH: SPR -> GPR
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// FMRDL: SPR -> GPR
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// FMRRS: SPR -> GPR
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// FMRX : SPR system reg -> GPR
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// FMSRR: GPR -> SPR
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// FMXR: GPR -> VFP Sstem reg
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// Int to FP:
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def VSITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a",
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[(set DPR:$dst, (arm_sitof SPR:$a))]> {
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let Inst{7} = 1;
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}
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def VSITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),(ins SPR:$a),
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IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a",
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[(set SPR:$dst, (arm_sitof SPR:$a))]> {
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let Inst{7} = 1;
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}
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def VUITOD : AVConv1I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a",
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[(set DPR:$dst, (arm_uitof SPR:$a))]>;
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def VUITOS : AVConv1In<0b11101011, 0b1000, 0b1010, (outs SPR:$dst),(ins SPR:$a),
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IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a",
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[(set SPR:$dst, (arm_uitof SPR:$a))]>;
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// FP to Int:
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// Always set Z bit in the instruction, i.e. "round towards zero" variants.
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def VTOSIZD : AVConv1I<0b11101011, 0b1101, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a",
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[(set SPR:$dst, (arm_ftosi DPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def VTOSIZS : AVConv1In<0b11101011, 0b1101, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a",
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[(set SPR:$dst, (arm_ftosi SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def VTOUIZD : AVConv1I<0b11101011, 0b1100, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a",
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[(set SPR:$dst, (arm_ftoui DPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def VTOUIZS : AVConv1In<0b11101011, 0b1100, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a",
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[(set SPR:$dst, (arm_ftoui SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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//===----------------------------------------------------------------------===//
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// FP FMA Operations.
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//
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def VMLAD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def VMLAS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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IIC_fpMAC32, "vmla", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def VNMLSD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def VNMLSS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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IIC_fpMAC32, "vnmls", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def VMLSD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst"> {
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let Inst{6} = 1;
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}
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def VMLSS : ASbIn<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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IIC_fpMAC32, "vmls", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst"> {
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let Inst{6} = 1;
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}
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def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, DPR:$b)),
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(VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
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(VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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|
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def VNMLAD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst"> {
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let Inst{6} = 1;
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}
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|
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def VNMLAS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
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IIC_fpMAC32, "vnmla", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst"> {
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let Inst{6} = 1;
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|
}
|
|
|
|
//===----------------------------------------------------------------------===//
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|
// FP Conditional moves.
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|
//
|
|
|
|
def VMOVDcc : ADuI<0b11101011, 0b0000, 0b0100,
|
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(outs DPR:$dst), (ins DPR:$false, DPR:$true),
|
|
IIC_fpUNA64, "vmov", ".f64\t$dst, $true",
|
|
[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
|
|
RegConstraint<"$false = $dst">;
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|
|
|
def VMOVScc : ASuI<0b11101011, 0b0000, 0b0100,
|
|
(outs SPR:$dst), (ins SPR:$false, SPR:$true),
|
|
IIC_fpUNA32, "vmov", ".f32\t$dst, $true",
|
|
[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
|
|
RegConstraint<"$false = $dst">;
|
|
|
|
def VNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
|
|
(outs DPR:$dst), (ins DPR:$false, DPR:$true),
|
|
IIC_fpUNA64, "vneg", ".f64\t$dst, $true",
|
|
[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
|
|
RegConstraint<"$false = $dst">;
|
|
|
|
def VNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
|
|
(outs SPR:$dst), (ins SPR:$false, SPR:$true),
|
|
IIC_fpUNA32, "vneg", ".f32\t$dst, $true",
|
|
[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
|
|
RegConstraint<"$false = $dst">;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Misc.
|
|
//
|
|
|
|
// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
|
|
// to APSR.
|
|
let Defs = [CPSR], Uses = [FPSCR] in
|
|
def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
|
|
"\tapsr_nzcv, fpscr",
|
|
[(arm_fmstat)]> {
|
|
let Inst{27-20} = 0b11101111;
|
|
let Inst{19-16} = 0b0001;
|
|
let Inst{15-12} = 0b1111;
|
|
let Inst{11-8} = 0b1010;
|
|
let Inst{7} = 0;
|
|
let Inst{4} = 1;
|
|
}
|
|
|
|
|
|
// Materialize FP immediates. VFP3 only.
|
|
let isReMaterializable = 1 in {
|
|
def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
|
|
VFPMiscFrm, IIC_VMOVImm,
|
|
"vmov", ".f64\t$dst, $imm",
|
|
[(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
|
|
let Inst{27-23} = 0b11101;
|
|
let Inst{21-20} = 0b11;
|
|
let Inst{11-9} = 0b101;
|
|
let Inst{8} = 1;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
|
|
def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
|
|
VFPMiscFrm, IIC_VMOVImm,
|
|
"vmov", ".f32\t$dst, $imm",
|
|
[(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
|
|
let Inst{27-23} = 0b11101;
|
|
let Inst{21-20} = 0b11;
|
|
let Inst{11-9} = 0b101;
|
|
let Inst{8} = 0;
|
|
let Inst{7-4} = 0b0000;
|
|
}
|
|
}
|