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3bf12ab860
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.2 KiB
C++
44 lines
1.2 KiB
C++
//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMREGISTERINFO_H
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#define ARMREGISTERINFO_H
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#include "ARM.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "ARMBaseRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ARMBaseInstrInfo;
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class Type;
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namespace ARM {
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/// SubregIndex - The index of various subregister classes. Note that
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/// these indices must be kept in sync with the class indices in the
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/// ARMRegisterInfo.td file.
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enum SubregIndex {
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SSUBREG_0 = 1, SSUBREG_1 = 2, SSUBREG_2 = 3, SSUBREG_3 = 4,
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DSUBREG_0 = 5, DSUBREG_1 = 6
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};
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}
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struct ARMRegisterInfo : public ARMBaseRegisterInfo {
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public:
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ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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};
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} // end namespace llvm
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#endif
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