mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.7 KiB
LLVM
57 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: cls_8b:
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;CHECK: cls.8b
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%tmp1 = load <8 x i8>* %A
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%tmp3 = call <8 x i8> @llvm.arm64.neon.cls.v8i8(<8 x i8> %tmp1)
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @cls_16b(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: cls_16b:
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;CHECK: cls.16b
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%tmp1 = load <16 x i8>* %A
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%tmp3 = call <16 x i8> @llvm.arm64.neon.cls.v16i8(<16 x i8> %tmp1)
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ret <16 x i8> %tmp3
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}
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define <4 x i16> @cls_4h(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: cls_4h:
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;CHECK: cls.4h
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%tmp1 = load <4 x i16>* %A
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%tmp3 = call <4 x i16> @llvm.arm64.neon.cls.v4i16(<4 x i16> %tmp1)
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ret <4 x i16> %tmp3
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}
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define <8 x i16> @cls_8h(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: cls_8h:
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;CHECK: cls.8h
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%tmp1 = load <8 x i16>* %A
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%tmp3 = call <8 x i16> @llvm.arm64.neon.cls.v8i16(<8 x i16> %tmp1)
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ret <8 x i16> %tmp3
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}
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define <2 x i32> @cls_2s(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: cls_2s:
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;CHECK: cls.2s
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%tmp1 = load <2 x i32>* %A
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%tmp3 = call <2 x i32> @llvm.arm64.neon.cls.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp3
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}
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define <4 x i32> @cls_4s(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: cls_4s:
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;CHECK: cls.4s
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%tmp1 = load <4 x i32>* %A
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%tmp3 = call <4 x i32> @llvm.arm64.neon.cls.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp3
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}
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declare <8 x i8> @llvm.arm64.neon.cls.v8i8(<8 x i8>) nounwind readnone
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declare <16 x i8> @llvm.arm64.neon.cls.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm64.neon.cls.v4i16(<4 x i16>) nounwind readnone
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declare <8 x i16> @llvm.arm64.neon.cls.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm64.neon.cls.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm64.neon.cls.v4i32(<4 x i32>) nounwind readnone
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