mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-16 11:30:51 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
2.2 KiB
LLVM
57 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon -print-before=post-RA-sched %s -o - 2>&1 \
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; RUN: | FileCheck %s
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define void @vst(i8* %m, [4 x i64] %v) {
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entry:
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; CHECK: vst:
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; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
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%v0 = extractvalue [4 x i64] %v, 0
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%v1 = extractvalue [4 x i64] %v, 1
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%v2 = extractvalue [4 x i64] %v, 2
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%v3 = extractvalue [4 x i64] %v, 3
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%t0 = bitcast i64 %v0 to <8 x i8>
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%t1 = bitcast i64 %v1 to <8 x i8>
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%t2 = bitcast i64 %v2 to <8 x i8>
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%t3 = bitcast i64 %v3 to <8 x i8>
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%s0 = bitcast <8 x i8> %t0 to <1 x i64>
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%s1 = bitcast <8 x i8> %t1 to <1 x i64>
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%s2 = bitcast <8 x i8> %t2 to <1 x i64>
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%s3 = bitcast <8 x i8> %t3 to <1 x i64>
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%tmp0 = bitcast <1 x i64> %s2 to i64
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%tmp1 = bitcast <1 x i64> %s3 to i64
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%n0 = insertelement <2 x i64> undef, i64 %tmp0, i32 0
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%n1 = insertelement <2 x i64> %n0, i64 %tmp1, i32 1
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call void @llvm.arm.neon.vst4.v1i64(i8* %m, <1 x i64> %s0, <1 x i64> %s1, <1 x i64> %s2, <1 x i64> %s3, i32 8)
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call void @bar(<2 x i64> %n1)
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ret void
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}
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
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; CHECK: vtbx4:
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; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
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%tmp7 = load <8 x i8>, <8 x i8>* %C
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%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
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call void @bar2(%struct.__neon_int8x8x4_t %tmp2, <8 x i8> %tmp8)
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ret <8 x i8> %tmp8
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}
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declare void @llvm.arm.neon.vst4.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32)
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declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare void @bar2(%struct.__neon_int8x8x4_t, <8 x i8>)
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declare void @bar(<2 x i64> %arg)
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