mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
740 lines
23 KiB
LLVM
740 lines
23 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK --check-prefix=FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK --check-prefix=FUNC %s
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; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s
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;===------------------------------------------------------------------------===;
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; GLOBAL ADDRESS SPACE
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;===------------------------------------------------------------------------===;
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; Load an i8 value from the global address space.
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; FUNC-LABEL: {{^}}load_i8:
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; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: buffer_load_ubyte v{{[0-9]+}},
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define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%1 = load i8 addrspace(1)* %in
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%2 = zext i8 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i8_sext:
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; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600-CHECK: 24
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600-CHECK: 24
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; SI-CHECK: buffer_load_sbyte
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define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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entry:
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%0 = load i8 addrspace(1)* %in
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%1 = sext i8 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v2i8:
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; R600-CHECK: VTX_READ_8
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; R600-CHECK: VTX_READ_8
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; SI-CHECK: buffer_load_ubyte
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; SI-CHECK: buffer_load_ubyte
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define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) {
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entry:
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%0 = load <2 x i8> addrspace(1)* %in
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%1 = zext <2 x i8> %0 to <2 x i32>
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store <2 x i32> %1, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v2i8_sext:
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; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
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; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
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; R600-CHECK-DAG: 24
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; SI-CHECK: buffer_load_sbyte
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; SI-CHECK: buffer_load_sbyte
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define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) {
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entry:
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%0 = load <2 x i8> addrspace(1)* %in
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%1 = sext <2 x i8> %0 to <2 x i32>
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store <2 x i32> %1, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v4i8:
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; R600-CHECK: VTX_READ_8
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; R600-CHECK: VTX_READ_8
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; R600-CHECK: VTX_READ_8
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; R600-CHECK: VTX_READ_8
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; SI-CHECK: buffer_load_ubyte
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; SI-CHECK: buffer_load_ubyte
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; SI-CHECK: buffer_load_ubyte
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; SI-CHECK: buffer_load_ubyte
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define void @load_v4i8(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) {
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entry:
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%0 = load <4 x i8> addrspace(1)* %in
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%1 = zext <4 x i8> %0 to <4 x i32>
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store <4 x i32> %1, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v4i8_sext:
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; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
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; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
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; R600-CHECK-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]]
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; R600-CHECK-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]]
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]]
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; R600-CHECK-DAG: 24
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]]
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; R600-CHECK-DAG: 24
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; SI-CHECK: buffer_load_sbyte
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; SI-CHECK: buffer_load_sbyte
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; SI-CHECK: buffer_load_sbyte
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; SI-CHECK: buffer_load_sbyte
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define void @load_v4i8_sext(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) {
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entry:
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%0 = load <4 x i8> addrspace(1)* %in
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%1 = sext <4 x i8> %0 to <4 x i32>
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store <4 x i32> %1, <4 x i32> addrspace(1)* %out
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ret void
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}
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; Load an i16 value from the global address space.
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; FUNC-LABEL: {{^}}load_i16:
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; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: buffer_load_ushort
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define void @load_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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entry:
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%0 = load i16 addrspace(1)* %in
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%1 = zext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i16_sext:
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; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600-CHECK: 16
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600-CHECK: 16
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; SI-CHECK: buffer_load_sshort
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define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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entry:
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%0 = load i16 addrspace(1)* %in
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%1 = sext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v2i16:
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; R600-CHECK: VTX_READ_16
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; R600-CHECK: VTX_READ_16
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; SI-CHECK: buffer_load_ushort
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; SI-CHECK: buffer_load_ushort
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define void @load_v2i16(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
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entry:
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%0 = load <2 x i16> addrspace(1)* %in
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%1 = zext <2 x i16> %0 to <2 x i32>
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store <2 x i32> %1, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v2i16_sext:
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; R600-CHECK-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
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; R600-CHECK-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
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; R600-CHECK-DAG: 16
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; SI-CHECK: buffer_load_sshort
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; SI-CHECK: buffer_load_sshort
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define void @load_v2i16_sext(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
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entry:
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%0 = load <2 x i16> addrspace(1)* %in
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%1 = sext <2 x i16> %0 to <2 x i32>
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store <2 x i32> %1, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v4i16:
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; R600-CHECK: VTX_READ_16
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; R600-CHECK: VTX_READ_16
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; R600-CHECK: VTX_READ_16
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; R600-CHECK: VTX_READ_16
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; SI-CHECK: buffer_load_ushort
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; SI-CHECK: buffer_load_ushort
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; SI-CHECK: buffer_load_ushort
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; SI-CHECK: buffer_load_ushort
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define void @load_v4i16(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) {
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entry:
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%0 = load <4 x i16> addrspace(1)* %in
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%1 = zext <4 x i16> %0 to <4 x i32>
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store <4 x i32> %1, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v4i16_sext:
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; R600-CHECK-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
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; R600-CHECK-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
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; R600-CHECK-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]]
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; R600-CHECK-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]]
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]]
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; R600-CHECK-DAG: 16
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; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]]
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; R600-CHECK-DAG: 16
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; SI-CHECK: buffer_load_sshort
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; SI-CHECK: buffer_load_sshort
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; SI-CHECK: buffer_load_sshort
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; SI-CHECK: buffer_load_sshort
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define void @load_v4i16_sext(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) {
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entry:
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%0 = load <4 x i16> addrspace(1)* %in
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%1 = sext <4 x i16> %0 to <4 x i32>
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store <4 x i32> %1, <4 x i32> addrspace(1)* %out
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ret void
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}
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; load an i32 value from the global address space.
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; FUNC-LABEL: {{^}}load_i32:
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: buffer_load_dword v{{[0-9]+}}
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define void @load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = load i32 addrspace(1)* %in
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; load a f32 value from the global address space.
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; FUNC-LABEL: {{^}}load_f32:
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: buffer_load_dword v{{[0-9]+}}
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define void @load_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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entry:
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%0 = load float addrspace(1)* %in
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store float %0, float addrspace(1)* %out
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ret void
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}
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; load a v2f32 value from the global address space
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; FUNC-LABEL: {{^}}load_v2f32:
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; R600-CHECK: MEM_RAT
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; R600-CHECK: VTX_READ_64
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; SI-CHECK: buffer_load_dwordx2
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define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
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entry:
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%0 = load <2 x float> addrspace(1)* %in
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i64:
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; R600-CHECK: VTX_READ_64
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; SI-CHECK: buffer_load_dwordx2
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define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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entry:
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%0 = load i64 addrspace(1)* %in
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i64_sext:
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; R600-CHECK: MEM_RAT
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; R600-CHECK: MEM_RAT
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x
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; R600-CHECK: 31
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; SI-CHECK: buffer_load_dword
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define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = load i32 addrspace(1)* %in
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%1 = sext i32 %0 to i64
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i64_zext:
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; R600-CHECK: MEM_RAT
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; R600-CHECK: MEM_RAT
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define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = load i32 addrspace(1)* %in
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%1 = zext i32 %0 to i64
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v8i32:
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; R600-CHECK: VTX_READ_128
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; R600-CHECK: VTX_READ_128
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; XXX: We should be using DWORDX4 instructions on SI.
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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define void @load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) {
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entry:
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%0 = load <8 x i32> addrspace(1)* %in
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store <8 x i32> %0, <8 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_v16i32:
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; R600-CHECK: VTX_READ_128
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; R600-CHECK: VTX_READ_128
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; R600-CHECK: VTX_READ_128
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; R600-CHECK: VTX_READ_128
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; XXX: We should be using DWORDX4 instructions on SI.
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
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; SI-CHECK: buffer_load_dword
|
|
; SI-CHECK: buffer_load_dword
|
|
; SI-CHECK: buffer_load_dword
|
|
; SI-CHECK: buffer_load_dword
|
|
define void @load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) {
|
|
entry:
|
|
%0 = load <16 x i32> addrspace(1)* %in
|
|
store <16 x i32> %0, <16 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
;===------------------------------------------------------------------------===;
|
|
; CONSTANT ADDRESS SPACE
|
|
;===------------------------------------------------------------------------===;
|
|
|
|
; Load a sign-extended i8 value
|
|
; FUNC-LABEL: {{^}}load_const_i8_sext:
|
|
; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
|
|
; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
|
|
; R600-CHECK: 24
|
|
; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
|
|
; R600-CHECK: 24
|
|
; SI-CHECK: buffer_load_sbyte v{{[0-9]+}},
|
|
define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
|
|
entry:
|
|
%0 = load i8 addrspace(2)* %in
|
|
%1 = sext i8 %0 to i32
|
|
store i32 %1, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Load an aligned i8 value
|
|
; FUNC-LABEL: {{^}}load_const_i8_aligned:
|
|
; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
|
|
; SI-CHECK: buffer_load_ubyte v{{[0-9]+}},
|
|
define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
|
|
entry:
|
|
%0 = load i8 addrspace(2)* %in
|
|
%1 = zext i8 %0 to i32
|
|
store i32 %1, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Load an un-aligned i8 value
|
|
; FUNC-LABEL: {{^}}load_const_i8_unaligned:
|
|
; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
|
|
; SI-CHECK: buffer_load_ubyte v{{[0-9]+}},
|
|
define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
|
|
entry:
|
|
%0 = getelementptr i8 addrspace(2)* %in, i32 1
|
|
%1 = load i8 addrspace(2)* %0
|
|
%2 = zext i8 %1 to i32
|
|
store i32 %2, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Load a sign-extended i16 value
|
|
; FUNC-LABEL: {{^}}load_const_i16_sext:
|
|
; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
|
|
; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
|
|
; R600-CHECK: 16
|
|
; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
|
|
; R600-CHECK: 16
|
|
; SI-CHECK: buffer_load_sshort
|
|
define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
|
|
entry:
|
|
%0 = load i16 addrspace(2)* %in
|
|
%1 = sext i16 %0 to i32
|
|
store i32 %1, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Load an aligned i16 value
|
|
; FUNC-LABEL: {{^}}load_const_i16_aligned:
|
|
; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
|
|
; SI-CHECK: buffer_load_ushort
|
|
define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
|
|
entry:
|
|
%0 = load i16 addrspace(2)* %in
|
|
%1 = zext i16 %0 to i32
|
|
store i32 %1, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Load an un-aligned i16 value
|
|
; FUNC-LABEL: {{^}}load_const_i16_unaligned:
|
|
; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
|
|
; SI-CHECK: buffer_load_ushort
|
|
define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
|
|
entry:
|
|
%0 = getelementptr i16 addrspace(2)* %in, i32 1
|
|
%1 = load i16 addrspace(2)* %0
|
|
%2 = zext i16 %1 to i32
|
|
store i32 %2, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Load an i32 value from the constant address space.
|
|
; FUNC-LABEL: {{^}}load_const_addrspace_i32:
|
|
; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
|
|
|
|
; SI-CHECK: s_load_dword s{{[0-9]+}}
|
|
define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) {
|
|
entry:
|
|
%0 = load i32 addrspace(2)* %in
|
|
store i32 %0, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Load a f32 value from the constant address space.
|
|
; FUNC-LABEL: {{^}}load_const_addrspace_f32:
|
|
; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
|
|
|
|
; SI-CHECK: s_load_dword s{{[0-9]+}}
|
|
define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) {
|
|
%1 = load float addrspace(2)* %in
|
|
store float %1, float addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
;===------------------------------------------------------------------------===;
|
|
; LOCAL ADDRESS SPACE
|
|
;===------------------------------------------------------------------------===;
|
|
|
|
; Load an i8 value from the local address space.
|
|
; FUNC-LABEL: {{^}}load_i8_local:
|
|
; R600-CHECK: LDS_UBYTE_READ_RET
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_u8
|
|
define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) {
|
|
%1 = load i8 addrspace(3)* %in
|
|
%2 = zext i8 %1 to i32
|
|
store i32 %2, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_i8_sext_local:
|
|
; R600-CHECK: LDS_UBYTE_READ_RET
|
|
; R600-CHECK: ASHR
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_i8
|
|
define void @load_i8_sext_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load i8 addrspace(3)* %in
|
|
%1 = sext i8 %0 to i32
|
|
store i32 %1, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_v2i8_local:
|
|
; R600-CHECK: LDS_UBYTE_READ_RET
|
|
; R600-CHECK: LDS_UBYTE_READ_RET
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_u8
|
|
; SI-CHECK: ds_read_u8
|
|
define void @load_v2i8_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <2 x i8> addrspace(3)* %in
|
|
%1 = zext <2 x i8> %0 to <2 x i32>
|
|
store <2 x i32> %1, <2 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_v2i8_sext_local:
|
|
; R600-CHECK-DAG: LDS_UBYTE_READ_RET
|
|
; R600-CHECK-DAG: LDS_UBYTE_READ_RET
|
|
; R600-CHECK-DAG: ASHR
|
|
; R600-CHECK-DAG: ASHR
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_i8
|
|
; SI-CHECK: ds_read_i8
|
|
define void @load_v2i8_sext_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <2 x i8> addrspace(3)* %in
|
|
%1 = sext <2 x i8> %0 to <2 x i32>
|
|
store <2 x i32> %1, <2 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_v4i8_local:
|
|
; R600-CHECK: LDS_UBYTE_READ_RET
|
|
; R600-CHECK: LDS_UBYTE_READ_RET
|
|
; R600-CHECK: LDS_UBYTE_READ_RET
|
|
; R600-CHECK: LDS_UBYTE_READ_RET
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_u8
|
|
; SI-CHECK: ds_read_u8
|
|
; SI-CHECK: ds_read_u8
|
|
; SI-CHECK: ds_read_u8
|
|
define void @load_v4i8_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <4 x i8> addrspace(3)* %in
|
|
%1 = zext <4 x i8> %0 to <4 x i32>
|
|
store <4 x i32> %1, <4 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_v4i8_sext_local:
|
|
; R600-CHECK-DAG: LDS_UBYTE_READ_RET
|
|
; R600-CHECK-DAG: LDS_UBYTE_READ_RET
|
|
; R600-CHECK-DAG: LDS_UBYTE_READ_RET
|
|
; R600-CHECK-DAG: LDS_UBYTE_READ_RET
|
|
; R600-CHECK-DAG: ASHR
|
|
; R600-CHECK-DAG: ASHR
|
|
; R600-CHECK-DAG: ASHR
|
|
; R600-CHECK-DAG: ASHR
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_i8
|
|
; SI-CHECK: ds_read_i8
|
|
; SI-CHECK: ds_read_i8
|
|
; SI-CHECK: ds_read_i8
|
|
define void @load_v4i8_sext_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <4 x i8> addrspace(3)* %in
|
|
%1 = sext <4 x i8> %0 to <4 x i32>
|
|
store <4 x i32> %1, <4 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Load an i16 value from the local address space.
|
|
; FUNC-LABEL: {{^}}load_i16_local:
|
|
; R600-CHECK: LDS_USHORT_READ_RET
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_u16
|
|
define void @load_i16_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load i16 addrspace(3)* %in
|
|
%1 = zext i16 %0 to i32
|
|
store i32 %1, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_i16_sext_local:
|
|
; R600-CHECK: LDS_USHORT_READ_RET
|
|
; R600-CHECK: ASHR
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_i16
|
|
define void @load_i16_sext_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load i16 addrspace(3)* %in
|
|
%1 = sext i16 %0 to i32
|
|
store i32 %1, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_v2i16_local:
|
|
; R600-CHECK: LDS_USHORT_READ_RET
|
|
; R600-CHECK: LDS_USHORT_READ_RET
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_u16
|
|
; SI-CHECK: ds_read_u16
|
|
define void @load_v2i16_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <2 x i16> addrspace(3)* %in
|
|
%1 = zext <2 x i16> %0 to <2 x i32>
|
|
store <2 x i32> %1, <2 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_v2i16_sext_local:
|
|
; R600-CHECK-DAG: LDS_USHORT_READ_RET
|
|
; R600-CHECK-DAG: LDS_USHORT_READ_RET
|
|
; R600-CHECK-DAG: ASHR
|
|
; R600-CHECK-DAG: ASHR
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_i16
|
|
; SI-CHECK: ds_read_i16
|
|
define void @load_v2i16_sext_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <2 x i16> addrspace(3)* %in
|
|
%1 = sext <2 x i16> %0 to <2 x i32>
|
|
store <2 x i32> %1, <2 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_v4i16_local:
|
|
; R600-CHECK: LDS_USHORT_READ_RET
|
|
; R600-CHECK: LDS_USHORT_READ_RET
|
|
; R600-CHECK: LDS_USHORT_READ_RET
|
|
; R600-CHECK: LDS_USHORT_READ_RET
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_u16
|
|
; SI-CHECK: ds_read_u16
|
|
; SI-CHECK: ds_read_u16
|
|
; SI-CHECK: ds_read_u16
|
|
define void @load_v4i16_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <4 x i16> addrspace(3)* %in
|
|
%1 = zext <4 x i16> %0 to <4 x i32>
|
|
store <4 x i32> %1, <4 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}load_v4i16_sext_local:
|
|
; R600-CHECK-DAG: LDS_USHORT_READ_RET
|
|
; R600-CHECK-DAG: LDS_USHORT_READ_RET
|
|
; R600-CHECK-DAG: LDS_USHORT_READ_RET
|
|
; R600-CHECK-DAG: LDS_USHORT_READ_RET
|
|
; R600-CHECK-DAG: ASHR
|
|
; R600-CHECK-DAG: ASHR
|
|
; R600-CHECK-DAG: ASHR
|
|
; R600-CHECK-DAG: ASHR
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_i16
|
|
; SI-CHECK: ds_read_i16
|
|
; SI-CHECK: ds_read_i16
|
|
; SI-CHECK: ds_read_i16
|
|
define void @load_v4i16_sext_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <4 x i16> addrspace(3)* %in
|
|
%1 = sext <4 x i16> %0 to <4 x i32>
|
|
store <4 x i32> %1, <4 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; load an i32 value from the local address space.
|
|
; FUNC-LABEL: {{^}}load_i32_local:
|
|
; R600-CHECK: LDS_READ_RET
|
|
; SI-CHECK-NOT: s_wqm_b64
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_b32
|
|
define void @load_i32_local(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load i32 addrspace(3)* %in
|
|
store i32 %0, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; load a f32 value from the local address space.
|
|
; FUNC-LABEL: {{^}}load_f32_local:
|
|
; R600-CHECK: LDS_READ_RET
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_b32
|
|
define void @load_f32_local(float addrspace(1)* %out, float addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load float addrspace(3)* %in
|
|
store float %0, float addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; load a v2f32 value from the local address space
|
|
; FUNC-LABEL: {{^}}load_v2f32_local:
|
|
; R600-CHECK: LDS_READ_RET
|
|
; R600-CHECK: LDS_READ_RET
|
|
; SI-CHECK: s_mov_b32 m0
|
|
; SI-CHECK: ds_read_b64
|
|
define void @load_v2f32_local(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %in) {
|
|
entry:
|
|
%0 = load <2 x float> addrspace(3)* %in
|
|
store <2 x float> %0, <2 x float> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; Test loading a i32 and v2i32 value from the same base pointer.
|
|
; FUNC-LABEL: {{^}}load_i32_v2i32_local:
|
|
; R600-CHECK: LDS_READ_RET
|
|
; R600-CHECK: LDS_READ_RET
|
|
; R600-CHECK: LDS_READ_RET
|
|
; SI-CHECK-DAG: ds_read_b32
|
|
; SI-CHECK-DAG: ds_read2_b32
|
|
define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)* %in) {
|
|
%scalar = load i32 addrspace(3)* %in
|
|
%tmp0 = bitcast i32 addrspace(3)* %in to <2 x i32> addrspace(3)*
|
|
%vec_ptr = getelementptr <2 x i32> addrspace(3)* %tmp0, i32 2
|
|
%vec0 = load <2 x i32> addrspace(3)* %vec_ptr, align 4
|
|
%vec1 = insertelement <2 x i32> <i32 0, i32 0>, i32 %scalar, i32 0
|
|
%vec = add <2 x i32> %vec0, %vec1
|
|
store <2 x i32> %vec, <2 x i32> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
|
|
@lds = addrspace(3) global [512 x i32] undef, align 4
|
|
|
|
; On SI we need to make sure that the base offset is a register and not
|
|
; an immediate.
|
|
; FUNC-LABEL: {{^}}load_i32_local_const_ptr:
|
|
; SI-CHECK: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0
|
|
; SI-CHECK: ds_read_b32 v0, v[[ZERO]] offset:4
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; R600-CHECK: LDS_READ_RET
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define void @load_i32_local_const_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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entry:
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%tmp0 = getelementptr [512 x i32] addrspace(3)* @lds, i32 0, i32 1
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%tmp1 = load i32 addrspace(3)* %tmp0
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%tmp2 = getelementptr i32 addrspace(1)* %out, i32 1
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store i32 %tmp1, i32 addrspace(1)* %tmp2
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ret void
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}
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