mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-03 00:29:31 +00:00
ab4022f196
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31311 91177308-0d34-0410-b5e6-96231b3b80d8
468 lines
15 KiB
C++
Executable File
468 lines
15 KiB
C++
Executable File
//===-- X86ATTAsmPrinter.cpp - Convert X86 LLVM code to Intel assembly ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to AT&T format assembly
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// language. This printer is the output mechanism used by `llc'.
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//
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//===----------------------------------------------------------------------===//
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#include "X86ATTAsmPrinter.h"
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#include "X86.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86TargetMachine.h"
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#include "X86TargetAsmInfo.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Module.h"
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#include "llvm/Support/Mangler.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Target/TargetOptions.h"
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#include <iostream>
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using namespace llvm;
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/// getSectionForFunction - Return the section that we should emit the
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/// specified function body into.
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std::string X86ATTAsmPrinter::getSectionForFunction(const Function &F) const {
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switch (F.getLinkage()) {
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default: assert(0 && "Unknown linkage type!");
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case Function::InternalLinkage:
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case Function::DLLExportLinkage:
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case Function::ExternalLinkage:
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return TAI->getTextSection();
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case Function::WeakLinkage:
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case Function::LinkOnceLinkage:
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if (Subtarget->isTargetDarwin()) {
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return ".section __TEXT,__textcoal_nt,coalesced,pure_instructions";
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} else if (Subtarget->isTargetCygwin()) {
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return "\t.section\t.text$linkonce." + CurrentFnName + ",\"ax\"\n";
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} else {
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return "\t.section\t.llvm.linkonce.t." + CurrentFnName +
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",\"ax\",@progbits\n";
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}
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}
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}
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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///
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bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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if (Subtarget->isTargetDarwin() ||
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Subtarget->isTargetELF() ||
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Subtarget->isTargetCygwin()) {
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// Let PassManager know we need debug information and relay
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// the MachineDebugInfo address on to DwarfWriter.
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DW.SetDebugInfo(&getAnalysis<MachineDebugInfo>());
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}
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SetupMachineFunction(MF);
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O << "\n\n";
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// Print out constants referenced by the function
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EmitConstantPool(MF.getConstantPool());
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// Print out labels for the function.
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const Function *F = MF.getFunction();
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unsigned CC = F->getCallingConv();
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// Populate function information map. Actually, We don't want to populate
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// non-stdcall or non-fastcall functions' information right now.
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if (CC == CallingConv::X86_StdCall || CC == CallingConv::X86_FastCall)
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FunctionInfoMap[F] = *MF.getInfo<X86FunctionInfo>();
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X86SharedAsmPrinter::decorateName(CurrentFnName, F);
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SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
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switch (F->getLinkage()) {
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default: assert(0 && "Unknown linkage type!");
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case Function::InternalLinkage: // Symbols default to internal.
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EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
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break;
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case Function::DLLExportLinkage:
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DLLExportedFns.insert(Mang->makeNameProper(F->getName(), ""));
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//FALLS THROUGH
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case Function::ExternalLinkage:
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EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
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O << "\t.globl\t" << CurrentFnName << "\n";
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break;
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case Function::LinkOnceLinkage:
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case Function::WeakLinkage:
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if (Subtarget->isTargetDarwin()) {
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O << "\t.globl\t" << CurrentFnName << "\n";
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O << "\t.weak_definition\t" << CurrentFnName << "\n";
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} else if (Subtarget->isTargetCygwin()) {
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EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
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O << "\t.linkonce discard\n";
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O << "\t.globl " << CurrentFnName << "\n";
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} else {
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EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
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O << "\t.weak " << CurrentFnName << "\n";
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}
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break;
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}
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O << CurrentFnName << ":\n";
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// Add some workaround for linkonce linkage on Cygwin\MinGW
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if (Subtarget->isTargetCygwin() &&
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(F->getLinkage() == Function::LinkOnceLinkage ||
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F->getLinkage() == Function::WeakLinkage))
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O << "_llvm$workaround$fake$stub_" << CurrentFnName << ":\n";
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if (Subtarget->isTargetDarwin() ||
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Subtarget->isTargetELF() ||
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Subtarget->isTargetCygwin()) {
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// Emit pre-function debug information.
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DW.BeginFunction(&MF);
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}
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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if (I->pred_begin() != I->pred_end()) {
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printBasicBlockLabel(I, true);
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O << '\n';
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}
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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O << "\t";
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printMachineInstruction(II);
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}
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}
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// Print out jump tables referenced by the function.
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// Mac OS X requires that the jump table follow the function, so that the jump
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// table is part of the same atom that the function is in.
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EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
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if (TAI->hasDotTypeDotSizeDirective())
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O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
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if (Subtarget->isTargetDarwin() ||
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Subtarget->isTargetELF() ||
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Subtarget->isTargetCygwin()) {
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// Emit post-function debug information.
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DW.EndFunction();
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}
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// We didn't modify anything.
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return false;
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}
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void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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const char *Modifier) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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case MachineOperand::MO_Register: {
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assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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"Virtual registers should not make it this far!");
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O << '%';
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unsigned Reg = MO.getReg();
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if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
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MVT::ValueType VT = (strcmp(Modifier+6,"64") == 0) ?
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MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
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((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
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Reg = getX86SubSuperRegister(Reg, VT);
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}
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for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
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O << (char)tolower(*Name);
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return;
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}
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case MachineOperand::MO_Immediate:
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if (!Modifier || strcmp(Modifier, "debug") != 0)
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O << '$';
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O << MO.getImmedValue();
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return;
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case MachineOperand::MO_MachineBasicBlock:
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printBasicBlockLabel(MO.getMachineBasicBlock());
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return;
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case MachineOperand::MO_JumpTableIndex: {
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bool isMemOp = Modifier && !strcmp(Modifier, "mem");
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if (!isMemOp) O << '$';
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O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << "_"
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<< MO.getJumpTableIndex();
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if (X86PICStyle == PICStyle::Stub &&
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TM.getRelocationModel() == Reloc::PIC_)
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O << "-\"L" << getFunctionNumber() << "$pb\"";
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if (Subtarget->is64Bit())
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O << "(%rip)";
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return;
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}
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case MachineOperand::MO_ConstantPoolIndex: {
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bool isMemOp = Modifier && !strcmp(Modifier, "mem");
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if (!isMemOp) O << '$';
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O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
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<< MO.getConstantPoolIndex();
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if (X86PICStyle == PICStyle::Stub &&
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TM.getRelocationModel() == Reloc::PIC_)
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O << "-\"L" << getFunctionNumber() << "$pb\"";
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int Offset = MO.getOffset();
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if (Offset > 0)
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O << "+" << Offset;
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else if (Offset < 0)
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O << Offset;
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if (Subtarget->is64Bit())
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O << "(%rip)";
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return;
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}
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case MachineOperand::MO_GlobalAddress: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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bool isMemOp = Modifier && !strcmp(Modifier, "mem");
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if (!isMemOp && !isCallOp) O << '$';
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GlobalValue *GV = MO.getGlobal();
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std::string Name = Mang->getValueName(GV);
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bool isExt = (GV->isExternal() || GV->hasWeakLinkage() ||
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GV->hasLinkOnceLinkage());
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X86SharedAsmPrinter::decorateName(Name, GV);
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if (X86PICStyle == PICStyle::Stub &&
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TM.getRelocationModel() != Reloc::Static) {
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// Link-once, External, or Weakly-linked global variables need
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// non-lazily-resolved stubs
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if (isExt) {
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// Dynamically-resolved functions need a stub for the function.
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if (isCallOp && isa<Function>(GV)) {
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FnStubs.insert(Name);
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O << "L" << Name << "$stub";
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} else {
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GVStubs.insert(Name);
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O << "L" << Name << "$non_lazy_ptr";
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}
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} else {
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if (GV->hasDLLImportLinkage()) {
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O << "__imp_";
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}
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O << Name;
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}
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if (!isCallOp && TM.getRelocationModel() == Reloc::PIC_)
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O << "-\"L" << getFunctionNumber() << "$pb\"";
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} else {
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if (GV->hasDLLImportLinkage()) {
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O << "__imp_";
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}
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O << Name;
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}
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int Offset = MO.getOffset();
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if (Offset > 0)
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O << "+" << Offset;
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else if (Offset < 0)
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O << Offset;
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if (!isCallOp &&
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Subtarget->is64Bit()) {
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if (isExt && TM.getRelocationModel() != Reloc::Static)
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O << "@GOTPCREL";
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O << "(%rip)";
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}
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return;
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}
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case MachineOperand::MO_ExternalSymbol: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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if (isCallOp &&
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X86PICStyle == PICStyle::Stub &&
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TM.getRelocationModel() != Reloc::Static) {
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std::string Name(TAI->getGlobalPrefix());
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Name += MO.getSymbolName();
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FnStubs.insert(Name);
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O << "L" << Name << "$stub";
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return;
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}
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if (!isCallOp) O << '$';
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O << TAI->getGlobalPrefix() << MO.getSymbolName();
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if (!isCallOp &&
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Subtarget->is64Bit())
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O << "(%rip)";
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return;
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}
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default:
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O << "<unknown operand type>"; return;
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}
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}
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void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
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unsigned char value = MI->getOperand(Op).getImmedValue();
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assert(value <= 7 && "Invalid ssecc argument!");
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switch (value) {
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case 0: O << "eq"; break;
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case 1: O << "lt"; break;
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case 2: O << "le"; break;
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case 3: O << "unord"; break;
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case 4: O << "neq"; break;
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case 5: O << "nlt"; break;
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case 6: O << "nle"; break;
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case 7: O << "ord"; break;
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}
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}
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void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
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const char *Modifier){
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assert(isMem(MI, Op) && "Invalid memory reference!");
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const MachineOperand &BaseReg = MI->getOperand(Op);
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int ScaleVal = MI->getOperand(Op+1).getImmedValue();
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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const MachineOperand &DispSpec = MI->getOperand(Op+3);
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if (BaseReg.isFrameIndex()) {
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O << "[frame slot #" << BaseReg.getFrameIndex();
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if (DispSpec.getImmedValue())
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O << " + " << DispSpec.getImmedValue();
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O << "]";
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return;
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}
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if (DispSpec.isGlobalAddress() ||
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DispSpec.isConstantPoolIndex() ||
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DispSpec.isJumpTableIndex()) {
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printOperand(MI, Op+3, "mem");
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} else {
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int DispVal = DispSpec.getImmedValue();
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if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
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O << DispVal;
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}
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if (IndexReg.getReg() || BaseReg.getReg()) {
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O << "(";
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if (BaseReg.getReg()) {
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printOperand(MI, Op, Modifier);
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}
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if (IndexReg.getReg()) {
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O << ",";
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printOperand(MI, Op+2, Modifier);
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if (ScaleVal != 1)
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O << "," << ScaleVal;
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}
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O << ")";
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}
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}
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void X86ATTAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
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O << "\"L" << getFunctionNumber() << "$pb\"\n";
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O << "\"L" << getFunctionNumber() << "$pb\":";
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}
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bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
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const char Mode) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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unsigned Reg = MO.getReg();
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switch (Mode) {
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default: return true; // Unknown mode.
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case 'b': // Print QImode register
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Reg = getX86SubSuperRegister(Reg, MVT::i8);
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break;
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case 'h': // Print QImode high register
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Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
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break;
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case 'w': // Print HImode register
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Reg = getX86SubSuperRegister(Reg, MVT::i16);
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break;
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case 'k': // Print SImode register
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Reg = getX86SubSuperRegister(Reg, MVT::i32);
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break;
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}
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O << '%';
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for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
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O << (char)tolower(*Name);
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return false;
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}
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/// PrintAsmOperand - Print out an operand for an inline asm expression.
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///
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bool X86ATTAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0) return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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default: return true; // Unknown modifier.
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case 'b': // Print QImode register
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case 'h': // Print QImode high register
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case 'w': // Print HImode register
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case 'k': // Print SImode register
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return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
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}
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}
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printOperand(MI, OpNo);
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return false;
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}
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bool X86ATTAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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printMemReference(MI, OpNo);
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return false;
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}
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/// printMachineInstruction -- Print out a single X86 LLVM instruction
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/// MI in Intel syntax to the current output stream.
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///
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void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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++EmittedInsts;
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// See if a truncate instruction can be turned into a nop.
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switch (MI->getOpcode()) {
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default: break;
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case X86::TRUNC_64to32:
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case X86::TRUNC_64to16:
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case X86::TRUNC_32to16:
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case X86::TRUNC_32to8:
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case X86::TRUNC_16to8:
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case X86::TRUNC_32_to8:
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case X86::TRUNC_16_to8: {
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const MachineOperand &MO0 = MI->getOperand(0);
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const MachineOperand &MO1 = MI->getOperand(1);
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unsigned Reg0 = MO0.getReg();
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unsigned Reg1 = MO1.getReg();
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unsigned Opc = MI->getOpcode();
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if (Opc == X86::TRUNC_64to32)
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Reg1 = getX86SubSuperRegister(Reg1, MVT::i32);
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else if (Opc == X86::TRUNC_32to16 || Opc == X86::TRUNC_64to16)
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Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
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else
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Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
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O << TAI->getCommentString() << " TRUNCATE ";
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if (Reg0 != Reg1)
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O << "\n\t";
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break;
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}
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case X86::PsMOVZX64rr32:
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O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
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break;
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}
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// Call the autogenerated instruction printer routines.
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printInstruction(MI);
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}
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// Include the auto-generated portion of the assembly writer.
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#include "X86GenAsmWriter.inc"
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