Jim Grosbach b29b4dd988 Tweak ARM assembly parsing and printing of MSR instruction. ... The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-19 22:45:10 +00:00
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ARM	Tweak ARM assembly parsing and printing of MSR instruction.	2011-07-19 22:45:10 +00:00
MBlaze
X86	Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.	2011-07-16 02:41:28 +00:00