mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-09 10:05:41 +00:00
80ada583f3
the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
3.5 KiB
C++
103 lines
3.5 KiB
C++
//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the PowerPC implementation of the TargetRegisterInfo
|
|
// class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef POWERPC32_REGISTERINFO_H
|
|
#define POWERPC32_REGISTERINFO_H
|
|
|
|
#include "llvm/ADT/DenseMap.h"
|
|
#include "PPC.h"
|
|
|
|
#define GET_REGINFO_HEADER
|
|
#include "PPCGenRegisterInfo.inc"
|
|
|
|
namespace llvm {
|
|
class PPCSubtarget;
|
|
class TargetInstrInfo;
|
|
class Type;
|
|
|
|
class PPCRegisterInfo : public PPCGenRegisterInfo {
|
|
DenseMap<unsigned, unsigned> ImmToIdxMap;
|
|
const PPCSubtarget &Subtarget;
|
|
public:
|
|
PPCRegisterInfo(const PPCSubtarget &SubTarget);
|
|
|
|
/// getPointerRegClass - Return the register class to use to hold pointers.
|
|
/// This is used for addressing modes.
|
|
virtual const TargetRegisterClass *
|
|
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
|
|
|
|
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
|
MachineFunction &MF) const;
|
|
|
|
/// Code Generation virtual methods...
|
|
const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
|
|
const uint32_t *getCallPreservedMask(CallingConv::ID CC) const;
|
|
const uint32_t *getNoPreservedMask() const;
|
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const;
|
|
|
|
/// We require the register scavenger.
|
|
bool requiresRegisterScavenging(const MachineFunction &MF) const {
|
|
return true;
|
|
}
|
|
|
|
bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
|
|
return true;
|
|
}
|
|
|
|
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
|
|
return true;
|
|
}
|
|
|
|
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
|
|
return true;
|
|
}
|
|
|
|
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
|
|
void lowerCRSpilling(MachineBasicBlock::iterator II,
|
|
unsigned FrameIndex) const;
|
|
void lowerCRRestore(MachineBasicBlock::iterator II,
|
|
unsigned FrameIndex) const;
|
|
void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
|
|
unsigned FrameIndex) const;
|
|
void lowerVRSAVERestore(MachineBasicBlock::iterator II,
|
|
unsigned FrameIndex) const;
|
|
|
|
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
|
|
int &FrameIdx) const;
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, unsigned FIOperandNum,
|
|
RegScavenger *RS = NULL) const;
|
|
|
|
// Support for virtual base registers.
|
|
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
|
|
void materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
|
unsigned BaseReg, int FrameIdx,
|
|
int64_t Offset) const;
|
|
void resolveFrameIndex(MachineBasicBlock::iterator I,
|
|
unsigned BaseReg, int64_t Offset) const;
|
|
bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
|
|
|
|
// Debug information queries.
|
|
unsigned getFrameRegister(const MachineFunction &MF) const;
|
|
|
|
// Exception handling queries.
|
|
unsigned getEHExceptionRegister() const;
|
|
unsigned getEHHandlerRegister() const;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|