mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-28 04:33:05 +00:00
7517bbc91a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
3.0 KiB
TableGen
77 lines
3.0 KiB
TableGen
//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This is the top level entry point for the Hexagon target.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-independent interfaces which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Hexagon Subtarget features.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Hexagon Archtectures
|
|
def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
|
|
"Hexagon v2">;
|
|
def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
|
|
"Hexagon v3">;
|
|
def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4",
|
|
"Hexagon v4">;
|
|
def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5",
|
|
"Hexagon v5">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File, Calling Conv, Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
include "HexagonSchedule.td"
|
|
include "HexagonRegisterInfo.td"
|
|
include "HexagonCallingConv.td"
|
|
include "HexagonInstrInfo.td"
|
|
include "HexagonIntrinsics.td"
|
|
include "HexagonIntrinsicsDerived.td"
|
|
|
|
def HexagonInstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Hexagon processors supported.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class Proc<string Name, ProcessorItineraries Itin,
|
|
list<SubtargetFeature> Features>
|
|
: Processor<Name, Itin, Features>;
|
|
|
|
def : Proc<"hexagonv2", HexagonItineraries, [ArchV2]>;
|
|
def : Proc<"hexagonv3", HexagonItineraries, [ArchV2, ArchV3]>;
|
|
def : Proc<"hexagonv4", HexagonItinerariesV4, [ArchV2, ArchV3, ArchV4]>;
|
|
def : Proc<"hexagonv5", HexagonItinerariesV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
|
|
|
|
|
|
// Hexagon Uses the MC printer for assembler output, so make sure the TableGen
|
|
// AsmWriter bits get associated with the correct class.
|
|
def HexagonAsmWriter : AsmWriter {
|
|
string AsmWriterClassName = "InstPrinter";
|
|
bit isMCAsmWriter = 1;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Declare the target which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def Hexagon : Target {
|
|
// Pull in Instruction Info:
|
|
let InstructionSet = HexagonInstrInfo;
|
|
|
|
let AssemblyWriters = [HexagonAsmWriter];
|
|
}
|