mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
eebc8a1bc5
#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8
372 lines
18 KiB
TableGen
372 lines
18 KiB
TableGen
//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 MMX instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction templates
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//===----------------------------------------------------------------------===//
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// MMXI - MMX instructions with TB prefix.
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// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
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class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
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class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
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// Some 'special' instructions
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def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
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"#IMPLICIT_DEF $dst",
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[(set VR64:$dst, (v8i8 (undef)))]>,
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Requires<[HasMMX]>;
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// 64-bit vector undef's.
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def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
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def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
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def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
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def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
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//===----------------------------------------------------------------------===//
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// MMX Pattern Fragments
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//===----------------------------------------------------------------------===//
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def loadv1i64 : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
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def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
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def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
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def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
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//===----------------------------------------------------------------------===//
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// MMX Multiclasses
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//===----------------------------------------------------------------------===//
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let isTwoAddress = 1 in {
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// MMXI_binop_rm - Simple MMX binary operator.
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multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, bit Commutable = 0> {
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def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
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let isCommutable = Commutable;
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}
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def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
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(bitconvert
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(loadv1i64 addr:$src2)))))]>;
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}
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multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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bit Commutable = 0> {
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def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
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let isCommutable = Commutable;
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}
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def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (loadv1i64 addr:$src2))))]>;
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}
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// MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
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//
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// FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
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// to collapse (bitconvert VT to VT) into its operand.
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//
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multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
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bit Commutable = 0> {
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def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
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let isCommutable = Commutable;
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}
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def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(OpNode VR64:$src1,(loadv1i64 addr:$src2)))]>;
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}
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multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr, Intrinsic IntId> {
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def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
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def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (loadv1i64 addr:$src2))))]>;
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def ri : MMXIi8<opc2, ImmForm, (ops VR64:$dst, VR64:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(scalar_to_vector (i32 imm:$src2))))]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// MMX EMMS Instruction
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//===----------------------------------------------------------------------===//
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def MMX_EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
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//===----------------------------------------------------------------------===//
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// MMX Scalar Instructions
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
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defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
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defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
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defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
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defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
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defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
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defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
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defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
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defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
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defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
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defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
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defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
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defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
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defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
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defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
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defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>;
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defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
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// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
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// MMX_PSHUF*, MMX_SHUFP* etc. imm.
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def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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}]>;
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def MMX_splat_mask : PatLeaf<(build_vector), [{
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return X86::isSplatMask(N);
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}], MMX_SHUFFLE_get_shuf_imm>;
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def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKHMask(N);
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}]>;
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let isTwoAddress = 1 in {
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def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1,
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(bc_v8i8 (loadv1i64 addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1,
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(bc_v4i16 (loadv1i64 addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v1i64 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v1i64 (vector_shuffle VR64:$src1,
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(loadv1i64 addr:$src2),
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MMX_UNPCKH_shuffle_mask)))]>;
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}
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// Logical Instructions
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defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
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defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
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defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
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let isTwoAddress = 1 in {
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def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"pandn {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
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VR64:$src2)))]>;
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def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"pandn {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
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(load addr:$src2))))]>;
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}
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// Shift Instructions
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defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
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int_x86_mmx_psrl_w>;
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defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
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int_x86_mmx_psrl_d>;
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defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
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int_x86_mmx_psrl_q>;
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defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
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int_x86_mmx_psll_w>;
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defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
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int_x86_mmx_psll_d>;
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defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
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int_x86_mmx_psll_q>;
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defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
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int_x86_mmx_psra_w>;
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defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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int_x86_mmx_psra_d>;
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// Pack instructions
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defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
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defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
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defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
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// Move Instructions
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def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
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"movd {$src, $dst|$dst, $src}", []>;
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def MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
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"movd {$src, $dst|$dst, $src}", []>;
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def MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
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"movd {$src, $dst|$dst, $src}", []>;
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def MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
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"movq {$src, $dst|$dst, $src}", []>;
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def MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
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"movq {$src, $dst|$dst, $src}",
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[(set VR64:$dst, (loadv1i64 addr:$src))]>;
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def MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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"movq {$src, $dst|$dst, $src}",
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[(store (v1i64 VR64:$src), addr:$dst)]>;
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// Conversion instructions
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def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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// Shuffle and unpack instructions
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def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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// Misc.
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def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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"movntq {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
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"maskmovq {$mask, $src|$src, $mask}", []>, TB,
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Requires<[HasMMX]>;
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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//===----------------------------------------------------------------------===//
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// Alias instructions that map zero vector to pxor.
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// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
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let isReMaterializable = 1 in {
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def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
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"pxor $dst, $dst",
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[(set VR64:$dst, (v1i64 immAllZerosV))]>;
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}
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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// Store 64-bit integer vector values.
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def : Pat<(store (v8i8 VR64:$src), addr:$dst),
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(MOVQ64mr addr:$dst, VR64:$src)>;
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def : Pat<(store (v4i16 VR64:$src), addr:$dst),
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(MOVQ64mr addr:$dst, VR64:$src)>;
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def : Pat<(store (v2i32 VR64:$src), addr:$dst),
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(MOVQ64mr addr:$dst, VR64:$src)>;
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|
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// 128-bit vector all zero's.
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def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
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def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
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def : Pat<(v2i32 immAllZerosV), (MMX_V_SET0)>;
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def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
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|
|
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// Bit convert.
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def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
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def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
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def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
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def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
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def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
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def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
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|
def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
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|
def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
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|
def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
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|
def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
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|
def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
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|
def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
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|
|
|
// Splat v1i64
|
|
let AddedComplexity = 10 in {
|
|
def : Pat<(vector_shuffle (v1i64 VR64:$src), (undef),
|
|
MMX_splat_mask:$sm),
|
|
(MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
|
|
def : Pat<(vector_shuffle (v1i64 VR64:$src), (undef),
|
|
MMX_UNPCKH_shuffle_mask:$sm),
|
|
(MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
|
|
}
|
|
|
|
def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
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|
|
|
// Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower 8 or
|
|
// 16-bits matter.
|
|
def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MOVD64rr GR32:$src)>;
|
|
def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MOVD64rr GR32:$src)>;
|