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it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
180 lines
7.1 KiB
C++
180 lines
7.1 KiB
C++
//===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAGSDNodes class, which implements
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// scheduling for an SDNode-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SCHEDULEDAGSDNODES_H
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#define SCHEDULEDAGSDNODES_H
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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namespace llvm {
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/// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
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///
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/// Edges between SUnits are initially based on edges in the SelectionDAG,
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/// and additional edges can be added by the schedulers as heuristics.
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/// SDNodes such as Constants, Registers, and a few others that are not
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/// interesting to schedulers are not allocated SUnits.
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///
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/// SDNodes with MVT::Flag operands are grouped along with the flagged
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/// nodes into a single SUnit so that they are scheduled together.
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///
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/// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
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/// edges. Physical register dependence information is not carried in
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/// the DAG and must be handled explicitly by schedulers.
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///
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class ScheduleDAGSDNodes : public ScheduleDAG {
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public:
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SelectionDAG *DAG; // DAG of the current basic block
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explicit ScheduleDAGSDNodes(MachineFunction &mf);
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virtual ~ScheduleDAGSDNodes() {}
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/// Run - perform scheduling.
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///
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void Run(SelectionDAG *dag, MachineBasicBlock *bb,
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MachineBasicBlock::iterator insertPos);
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/// isPassiveNode - Return true if the node is a non-scheduled leaf.
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///
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static bool isPassiveNode(SDNode *Node) {
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if (isa<ConstantSDNode>(Node)) return true;
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if (isa<ConstantFPSDNode>(Node)) return true;
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if (isa<RegisterSDNode>(Node)) return true;
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if (isa<GlobalAddressSDNode>(Node)) return true;
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if (isa<BasicBlockSDNode>(Node)) return true;
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if (isa<FrameIndexSDNode>(Node)) return true;
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if (isa<ConstantPoolSDNode>(Node)) return true;
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if (isa<JumpTableSDNode>(Node)) return true;
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if (isa<ExternalSymbolSDNode>(Node)) return true;
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if (isa<MemOperandSDNode>(Node)) return true;
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if (Node->getOpcode() == ISD::EntryToken) return true;
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return false;
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}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *NewSUnit(SDNode *N) {
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#ifndef NDEBUG
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const SUnit *Addr = 0;
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if (!SUnits.empty())
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Addr = &SUnits[0];
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#endif
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SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
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assert((Addr == 0 || Addr == &SUnits[0]) &&
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"SUnits std::vector reallocated on the fly!");
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SUnits.back().OrigNode = &SUnits.back();
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return &SUnits.back();
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}
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/// Clone - Creates a clone of the specified SUnit. It does not copy the
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/// predecessors / successors info nor the temporary scheduling states.
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///
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SUnit *Clone(SUnit *N);
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/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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/// are input. This SUnit graph is similar to the SelectionDAG, but
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/// excludes nodes that aren't interesting to scheduling, and represents
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/// flagged together nodes with a single SUnit.
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virtual void BuildSchedGraph();
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/// ComputeLatency - Compute node latency.
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///
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virtual void ComputeLatency(SUnit *SU);
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands
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/// (which do not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node);
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by special operands that describe memory references, then an
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/// optional chain operand, then flag operands. Compute the number of
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/// actual operands that will go into the resulting MachineInstr.
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static unsigned CountOperands(SDNode *Node);
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/// ComputeMemOperandsEnd - Find the index one past the last
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/// MemOperandSDNode operand
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static unsigned ComputeMemOperandsEnd(SDNode *Node);
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/// EmitNode - Generate machine code for an node and needed dependencies.
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/// VRBaseMap contains, for each already emitted node, the first virtual
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/// register number for the results of the node.
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///
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void EmitNode(SDNode *Node, bool IsClone, bool HasClone,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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virtual MachineBasicBlock *EmitSchedule();
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/// Schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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virtual void Schedule() = 0;
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virtual void dumpNode(const SUnit *SU) const;
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virtual std::string getGraphNodeLabel(const SUnit *SU) const;
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virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
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private:
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void EmitSubregNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS
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/// nodes.
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///
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void EmitCopyToRegClassNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
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/// getDstOfCopyToRegUse - If the only use of the specified result number of
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/// node is a CopyToReg, return its destination register. Return 0 otherwise.
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unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
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void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// AddRegisterOperand - Add the specified register as an operand to the
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/// specified machine instr. Insert register copies if the register is
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/// not in the required register class.
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void AddRegisterOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum, const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
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bool IsCloned, unsigned SrcReg,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II, bool IsClone,
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bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
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void BuildSchedUnits();
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void AddSchedEdges();
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};
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}
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#endif
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