mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ab849adec4
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.
The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).
Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that. The assembler and disassembler
are fully implemented and tested. However:
- CodeGen support causes miscompiles; test-suite runtime failures:
MultiSource/Benchmarks/FreeBench/distray/distray
MultiSource/Benchmarks/McCat/08-main/main
MultiSource/Benchmarks/Olden/voronoi/voronoi
MultiSource/Benchmarks/mafft/pairlocalalign
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
SingleSource/Benchmarks/CoyoteBench/almabench
SingleSource/Benchmarks/Misc/matmul_f64_4x4
- The lowering currently falls back to using Altivec instructions far more
than it should. Worse, there are some things that are scalarized through the
stack that shouldn't be.
- A lot of unnecessary copies make it past the optimizers, and this needs to
be fixed.
- Many more regression tests are needed.
Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
1575 lines
50 KiB
C++
1575 lines
50 KiB
C++
//===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "MCTargetDesc/PPCMCExpr.h"
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#include "PPCTargetStreamer.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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static unsigned RRegs[32] = {
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PPC::R0, PPC::R1, PPC::R2, PPC::R3,
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PPC::R4, PPC::R5, PPC::R6, PPC::R7,
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PPC::R8, PPC::R9, PPC::R10, PPC::R11,
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PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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PPC::R28, PPC::R29, PPC::R30, PPC::R31
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};
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static unsigned RRegsNoR0[32] = {
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PPC::ZERO,
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PPC::R1, PPC::R2, PPC::R3,
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PPC::R4, PPC::R5, PPC::R6, PPC::R7,
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PPC::R8, PPC::R9, PPC::R10, PPC::R11,
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PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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PPC::R28, PPC::R29, PPC::R30, PPC::R31
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};
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static unsigned XRegs[32] = {
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PPC::X0, PPC::X1, PPC::X2, PPC::X3,
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PPC::X4, PPC::X5, PPC::X6, PPC::X7,
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PPC::X8, PPC::X9, PPC::X10, PPC::X11,
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PPC::X12, PPC::X13, PPC::X14, PPC::X15,
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PPC::X16, PPC::X17, PPC::X18, PPC::X19,
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PPC::X20, PPC::X21, PPC::X22, PPC::X23,
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PPC::X24, PPC::X25, PPC::X26, PPC::X27,
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PPC::X28, PPC::X29, PPC::X30, PPC::X31
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};
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static unsigned XRegsNoX0[32] = {
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PPC::ZERO8,
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PPC::X1, PPC::X2, PPC::X3,
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PPC::X4, PPC::X5, PPC::X6, PPC::X7,
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PPC::X8, PPC::X9, PPC::X10, PPC::X11,
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PPC::X12, PPC::X13, PPC::X14, PPC::X15,
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PPC::X16, PPC::X17, PPC::X18, PPC::X19,
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PPC::X20, PPC::X21, PPC::X22, PPC::X23,
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PPC::X24, PPC::X25, PPC::X26, PPC::X27,
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PPC::X28, PPC::X29, PPC::X30, PPC::X31
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};
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static unsigned FRegs[32] = {
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PPC::F0, PPC::F1, PPC::F2, PPC::F3,
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PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11,
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PPC::F12, PPC::F13, PPC::F14, PPC::F15,
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PPC::F16, PPC::F17, PPC::F18, PPC::F19,
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PPC::F20, PPC::F21, PPC::F22, PPC::F23,
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PPC::F24, PPC::F25, PPC::F26, PPC::F27,
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PPC::F28, PPC::F29, PPC::F30, PPC::F31
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};
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static unsigned VRegs[32] = {
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PPC::V0, PPC::V1, PPC::V2, PPC::V3,
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PPC::V4, PPC::V5, PPC::V6, PPC::V7,
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PPC::V8, PPC::V9, PPC::V10, PPC::V11,
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PPC::V12, PPC::V13, PPC::V14, PPC::V15,
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PPC::V16, PPC::V17, PPC::V18, PPC::V19,
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PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27,
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PPC::V28, PPC::V29, PPC::V30, PPC::V31
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};
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static unsigned VSRegs[64] = {
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PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
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PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
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PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
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PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
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PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
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PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
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PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
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PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
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PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
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PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
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PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
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PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
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PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
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PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
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PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
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PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
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};
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static unsigned CRBITRegs[32] = {
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PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
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PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
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PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
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PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
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PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
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PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
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PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
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PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
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};
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static unsigned CRRegs[8] = {
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PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
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PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
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};
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// Evaluate an expression containing condition register
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// or condition register field symbols. Returns positive
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// value on success, or -1 on error.
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static int64_t
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EvaluateCRExpr(const MCExpr *E) {
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switch (E->getKind()) {
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case MCExpr::Target:
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return -1;
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case MCExpr::Constant: {
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int64_t Res = cast<MCConstantExpr>(E)->getValue();
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return Res < 0 ? -1 : Res;
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}
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case MCExpr::SymbolRef: {
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const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
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StringRef Name = SRE->getSymbol().getName();
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if (Name == "lt") return 0;
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if (Name == "gt") return 1;
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if (Name == "eq") return 2;
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if (Name == "so") return 3;
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if (Name == "un") return 3;
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if (Name == "cr0") return 0;
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if (Name == "cr1") return 1;
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if (Name == "cr2") return 2;
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if (Name == "cr3") return 3;
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if (Name == "cr4") return 4;
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if (Name == "cr5") return 5;
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if (Name == "cr6") return 6;
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if (Name == "cr7") return 7;
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return -1;
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}
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case MCExpr::Unary:
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return -1;
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case MCExpr::Binary: {
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const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
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int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
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int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
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int64_t Res;
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if (LHSVal < 0 || RHSVal < 0)
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return -1;
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switch (BE->getOpcode()) {
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default: return -1;
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case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
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case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
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}
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return Res < 0 ? -1 : Res;
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}
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}
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llvm_unreachable("Invalid expression kind!");
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}
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struct PPCOperand;
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class PPCAsmParser : public MCTargetAsmParser {
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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const MCInstrInfo &MII;
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bool IsPPC64;
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bool IsDarwin;
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool isPPC64() const { return IsPPC64; }
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bool isDarwin() const { return IsDarwin; }
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bool MatchRegisterName(const AsmToken &Tok,
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unsigned &RegNo, int64_t &IntVal);
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virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
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PPCMCExpr::VariantKind &Variant);
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const MCExpr *FixupVariantKind(const MCExpr *E);
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bool ParseExpression(const MCExpr *&EVal);
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bool ParseDarwinExpression(const MCExpr *&EVal);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool ParseDirectiveTC(unsigned Size, SMLoc L);
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bool ParseDirectiveMachine(SMLoc L);
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bool ParseDarwinDirectiveMachine(SMLoc L);
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out, unsigned &ErrorInfo,
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bool MatchingInlineAsm);
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void ProcessInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
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/// @name Auto-generated Match Functions
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/// {
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#define GET_ASSEMBLER_HEADER
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#include "PPCGenAsmMatcher.inc"
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/// }
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public:
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PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
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const MCInstrInfo &_MII)
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: MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
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// Check for 64-bit vs. 32-bit pointer mode.
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Triple TheTriple(STI.getTargetTriple());
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IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
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TheTriple.getArch() == Triple::ppc64le);
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IsDarwin = TheTriple.isMacOSX();
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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virtual bool ParseInstruction(ParseInstructionInfo &Info,
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StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
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virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
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MCSymbolRefExpr::VariantKind,
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MCContext &Ctx);
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};
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/// PPCOperand - Instances of this class represent a parsed PowerPC machine
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/// instruction.
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struct PPCOperand : public MCParsedAsmOperand {
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enum KindTy {
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Token,
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Immediate,
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Expression,
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TLSRegister
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} Kind;
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SMLoc StartLoc, EndLoc;
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bool IsPPC64;
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struct TokOp {
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const char *Data;
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unsigned Length;
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};
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struct ImmOp {
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int64_t Val;
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};
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struct ExprOp {
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const MCExpr *Val;
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int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
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};
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struct TLSRegOp {
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const MCSymbolRefExpr *Sym;
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};
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union {
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struct TokOp Tok;
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struct ImmOp Imm;
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struct ExprOp Expr;
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struct TLSRegOp TLSReg;
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};
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PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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public:
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PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
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Kind = o.Kind;
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StartLoc = o.StartLoc;
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EndLoc = o.EndLoc;
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IsPPC64 = o.IsPPC64;
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switch (Kind) {
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case Token:
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Tok = o.Tok;
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break;
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case Immediate:
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Imm = o.Imm;
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break;
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case Expression:
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Expr = o.Expr;
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break;
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case TLSRegister:
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TLSReg = o.TLSReg;
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break;
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}
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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/// isPPC64 - True if this operand is for an instruction in 64-bit mode.
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bool isPPC64() const { return IsPPC64; }
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int64_t getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCExpr *getExpr() const {
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assert(Kind == Expression && "Invalid access!");
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return Expr.Val;
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}
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int64_t getExprCRVal() const {
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assert(Kind == Expression && "Invalid access!");
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return Expr.CRVal;
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}
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const MCExpr *getTLSReg() const {
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assert(Kind == TLSRegister && "Invalid access!");
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return TLSReg.Sym;
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}
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unsigned getReg() const {
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assert(isRegNumber() && "Invalid access!");
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return (unsigned) Imm.Val;
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}
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unsigned getVSReg() const {
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assert(isVSRegNumber() && "Invalid access!");
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return (unsigned) Imm.Val;
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}
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unsigned getCCReg() const {
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assert(isCCRegNumber() && "Invalid access!");
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return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
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}
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unsigned getCRBit() const {
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assert(isCRBitNumber() && "Invalid access!");
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return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
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}
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unsigned getCRBitMask() const {
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assert(isCRBitMask() && "Invalid access!");
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return 7 - countTrailingZeros<uint64_t>(Imm.Val);
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}
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bool isToken() const { return Kind == Token; }
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bool isImm() const { return Kind == Immediate || Kind == Expression; }
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bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
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bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
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bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
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bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
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bool isU16Imm() const { return Kind == Expression ||
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(Kind == Immediate && isUInt<16>(getImm())); }
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bool isS16Imm() const { return Kind == Expression ||
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(Kind == Immediate && isInt<16>(getImm())); }
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bool isS16ImmX4() const { return Kind == Expression ||
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(Kind == Immediate && isInt<16>(getImm()) &&
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(getImm() & 3) == 0); }
|
|
bool isS17Imm() const { return Kind == Expression ||
|
|
(Kind == Immediate && isInt<17>(getImm())); }
|
|
bool isTLSReg() const { return Kind == TLSRegister; }
|
|
bool isDirectBr() const { return Kind == Expression ||
|
|
(Kind == Immediate && isInt<26>(getImm()) &&
|
|
(getImm() & 3) == 0); }
|
|
bool isCondBr() const { return Kind == Expression ||
|
|
(Kind == Immediate && isInt<16>(getImm()) &&
|
|
(getImm() & 3) == 0); }
|
|
bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
|
|
bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
|
|
bool isCCRegNumber() const { return (Kind == Expression
|
|
&& isUInt<3>(getExprCRVal())) ||
|
|
(Kind == Immediate
|
|
&& isUInt<3>(getImm())); }
|
|
bool isCRBitNumber() const { return (Kind == Expression
|
|
&& isUInt<5>(getExprCRVal())) ||
|
|
(Kind == Immediate
|
|
&& isUInt<5>(getImm())); }
|
|
bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
|
|
isPowerOf2_32(getImm()); }
|
|
bool isMem() const { return false; }
|
|
bool isReg() const { return false; }
|
|
|
|
void addRegOperands(MCInst &Inst, unsigned N) const {
|
|
llvm_unreachable("addRegOperands");
|
|
}
|
|
|
|
void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
|
|
}
|
|
|
|
void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
|
|
}
|
|
|
|
void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
|
|
}
|
|
|
|
void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
|
|
}
|
|
|
|
void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
|
|
if (isPPC64())
|
|
addRegG8RCOperands(Inst, N);
|
|
else
|
|
addRegGPRCOperands(Inst, N);
|
|
}
|
|
|
|
void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
|
|
if (isPPC64())
|
|
addRegG8RCNoX0Operands(Inst, N);
|
|
else
|
|
addRegGPRCNoR0Operands(Inst, N);
|
|
}
|
|
|
|
void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
|
|
}
|
|
|
|
void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
|
|
}
|
|
|
|
void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
|
|
}
|
|
|
|
void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
|
|
}
|
|
|
|
void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
|
|
}
|
|
|
|
void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
|
|
}
|
|
|
|
void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
|
|
}
|
|
|
|
void addImmOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
if (Kind == Immediate)
|
|
Inst.addOperand(MCOperand::CreateImm(getImm()));
|
|
else
|
|
Inst.addOperand(MCOperand::CreateExpr(getExpr()));
|
|
}
|
|
|
|
void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
if (Kind == Immediate)
|
|
Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
|
|
else
|
|
Inst.addOperand(MCOperand::CreateExpr(getExpr()));
|
|
}
|
|
|
|
void addTLSRegOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
|
|
}
|
|
|
|
StringRef getToken() const {
|
|
assert(Kind == Token && "Invalid access!");
|
|
return StringRef(Tok.Data, Tok.Length);
|
|
}
|
|
|
|
virtual void print(raw_ostream &OS) const;
|
|
|
|
static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
|
|
PPCOperand *Op = new PPCOperand(Token);
|
|
Op->Tok.Data = Str.data();
|
|
Op->Tok.Length = Str.size();
|
|
Op->StartLoc = S;
|
|
Op->EndLoc = S;
|
|
Op->IsPPC64 = IsPPC64;
|
|
return Op;
|
|
}
|
|
|
|
static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
|
|
bool IsPPC64) {
|
|
// Allocate extra memory for the string and copy it.
|
|
void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
|
|
PPCOperand *Op = new (Mem) PPCOperand(Token);
|
|
Op->Tok.Data = (const char *)(Op + 1);
|
|
Op->Tok.Length = Str.size();
|
|
std::memcpy((char *)(Op + 1), Str.data(), Str.size());
|
|
Op->StartLoc = S;
|
|
Op->EndLoc = S;
|
|
Op->IsPPC64 = IsPPC64;
|
|
return Op;
|
|
}
|
|
|
|
static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
|
|
PPCOperand *Op = new PPCOperand(Immediate);
|
|
Op->Imm.Val = Val;
|
|
Op->StartLoc = S;
|
|
Op->EndLoc = E;
|
|
Op->IsPPC64 = IsPPC64;
|
|
return Op;
|
|
}
|
|
|
|
static PPCOperand *CreateExpr(const MCExpr *Val,
|
|
SMLoc S, SMLoc E, bool IsPPC64) {
|
|
PPCOperand *Op = new PPCOperand(Expression);
|
|
Op->Expr.Val = Val;
|
|
Op->Expr.CRVal = EvaluateCRExpr(Val);
|
|
Op->StartLoc = S;
|
|
Op->EndLoc = E;
|
|
Op->IsPPC64 = IsPPC64;
|
|
return Op;
|
|
}
|
|
|
|
static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
|
|
SMLoc S, SMLoc E, bool IsPPC64) {
|
|
PPCOperand *Op = new PPCOperand(TLSRegister);
|
|
Op->TLSReg.Sym = Sym;
|
|
Op->StartLoc = S;
|
|
Op->EndLoc = E;
|
|
Op->IsPPC64 = IsPPC64;
|
|
return Op;
|
|
}
|
|
|
|
static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
|
|
SMLoc S, SMLoc E, bool IsPPC64) {
|
|
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
|
|
return CreateImm(CE->getValue(), S, E, IsPPC64);
|
|
|
|
if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
|
|
if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
|
|
return CreateTLSReg(SRE, S, E, IsPPC64);
|
|
|
|
return CreateExpr(Val, S, E, IsPPC64);
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace.
|
|
|
|
void PPCOperand::print(raw_ostream &OS) const {
|
|
switch (Kind) {
|
|
case Token:
|
|
OS << "'" << getToken() << "'";
|
|
break;
|
|
case Immediate:
|
|
OS << getImm();
|
|
break;
|
|
case Expression:
|
|
getExpr()->print(OS);
|
|
break;
|
|
case TLSRegister:
|
|
getTLSReg()->print(OS);
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
void PPCAsmParser::
|
|
ProcessInstruction(MCInst &Inst,
|
|
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
int Opcode = Inst.getOpcode();
|
|
switch (Opcode) {
|
|
case PPC::LAx: {
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(PPC::LA);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(2));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SUBI: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(PPC::ADDI);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(-N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SUBIS: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(PPC::ADDIS);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(-N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SUBIC: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(PPC::ADDIC);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(-N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SUBICo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(PPC::ADDICo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(-N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::EXTLWI:
|
|
case PPC::EXTLWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N - 1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::EXTRWI:
|
|
case PPC::EXTRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B + N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::INSLWI:
|
|
case PPC::INSLWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - B));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::INSRWI:
|
|
case PPC::INSRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::ROTRWI:
|
|
case PPC::ROTRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SLWI:
|
|
case PPC::SLWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SRWI:
|
|
case PPC::SRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(32 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::CLRRWI:
|
|
case PPC::CLRRWIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::CLRLSLWI:
|
|
case PPC::CLRLSLWIo: {
|
|
MCInst TmpInst;
|
|
int64_t B = Inst.getOperand(2).getImm();
|
|
int64_t N = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(31 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::EXTLDI:
|
|
case PPC::EXTLDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N - 1));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::EXTRDI:
|
|
case PPC::EXTRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B + N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(64 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::INSRDI:
|
|
case PPC::INSRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
int64_t B = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::ROTRDI:
|
|
case PPC::ROTRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(64 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SLDI:
|
|
case PPC::SLDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(63 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::SRDI:
|
|
case PPC::SRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(64 - N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::CLRRDI:
|
|
case PPC::CLRRDIo: {
|
|
MCInst TmpInst;
|
|
int64_t N = Inst.getOperand(2).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
TmpInst.addOperand(MCOperand::CreateImm(63 - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
case PPC::CLRLSLDI:
|
|
case PPC::CLRLSLDIo: {
|
|
MCInst TmpInst;
|
|
int64_t B = Inst.getOperand(2).getImm();
|
|
int64_t N = Inst.getOperand(3).getImm();
|
|
TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
|
|
TmpInst.addOperand(Inst.getOperand(0));
|
|
TmpInst.addOperand(Inst.getOperand(1));
|
|
TmpInst.addOperand(MCOperand::CreateImm(N));
|
|
TmpInst.addOperand(MCOperand::CreateImm(B - N));
|
|
Inst = TmpInst;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
bool PPCAsmParser::
|
|
MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
MCStreamer &Out, unsigned &ErrorInfo,
|
|
bool MatchingInlineAsm) {
|
|
MCInst Inst;
|
|
|
|
switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
|
|
default: break;
|
|
case Match_Success:
|
|
// Post-process instructions (typically extended mnemonics)
|
|
ProcessInstruction(Inst, Operands);
|
|
Inst.setLoc(IDLoc);
|
|
Out.EmitInstruction(Inst, STI);
|
|
return false;
|
|
case Match_MissingFeature:
|
|
return Error(IDLoc, "instruction use requires an option to be enabled");
|
|
case Match_MnemonicFail:
|
|
return Error(IDLoc, "unrecognized instruction mnemonic");
|
|
case Match_InvalidOperand: {
|
|
SMLoc ErrorLoc = IDLoc;
|
|
if (ErrorInfo != ~0U) {
|
|
if (ErrorInfo >= Operands.size())
|
|
return Error(IDLoc, "too few operands for instruction");
|
|
|
|
ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
|
|
if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
|
|
}
|
|
|
|
return Error(ErrorLoc, "invalid operand for instruction");
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Implement any new match types added!");
|
|
}
|
|
|
|
bool PPCAsmParser::
|
|
MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
|
|
if (Tok.is(AsmToken::Identifier)) {
|
|
StringRef Name = Tok.getString();
|
|
|
|
if (Name.equals_lower("lr")) {
|
|
RegNo = isPPC64()? PPC::LR8 : PPC::LR;
|
|
IntVal = 8;
|
|
return false;
|
|
} else if (Name.equals_lower("ctr")) {
|
|
RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
|
|
IntVal = 9;
|
|
return false;
|
|
} else if (Name.equals_lower("vrsave")) {
|
|
RegNo = PPC::VRSAVE;
|
|
IntVal = 256;
|
|
return false;
|
|
} else if (Name.startswith_lower("r") &&
|
|
!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
|
|
RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
|
|
return false;
|
|
} else if (Name.startswith_lower("f") &&
|
|
!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
|
|
RegNo = FRegs[IntVal];
|
|
return false;
|
|
} else if (Name.startswith_lower("v") &&
|
|
!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
|
|
RegNo = VRegs[IntVal];
|
|
return false;
|
|
} else if (Name.startswith_lower("cr") &&
|
|
!Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
|
|
RegNo = CRRegs[IntVal];
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool PPCAsmParser::
|
|
ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
StartLoc = Tok.getLoc();
|
|
EndLoc = Tok.getEndLoc();
|
|
RegNo = 0;
|
|
int64_t IntVal;
|
|
|
|
if (!MatchRegisterName(Tok, RegNo, IntVal)) {
|
|
Parser.Lex(); // Eat identifier token.
|
|
return false;
|
|
}
|
|
|
|
return Error(StartLoc, "invalid register name");
|
|
}
|
|
|
|
/// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
|
|
/// the expression and check for VK_PPC_LO/HI/HA
|
|
/// symbol variants. If all symbols with modifier use the same
|
|
/// variant, return the corresponding PPCMCExpr::VariantKind,
|
|
/// and a modified expression using the default symbol variant.
|
|
/// Otherwise, return NULL.
|
|
const MCExpr *PPCAsmParser::
|
|
ExtractModifierFromExpr(const MCExpr *E,
|
|
PPCMCExpr::VariantKind &Variant) {
|
|
MCContext &Context = getParser().getContext();
|
|
Variant = PPCMCExpr::VK_PPC_None;
|
|
|
|
switch (E->getKind()) {
|
|
case MCExpr::Target:
|
|
case MCExpr::Constant:
|
|
return 0;
|
|
|
|
case MCExpr::SymbolRef: {
|
|
const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
|
|
|
|
switch (SRE->getKind()) {
|
|
case MCSymbolRefExpr::VK_PPC_LO:
|
|
Variant = PPCMCExpr::VK_PPC_LO;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HI:
|
|
Variant = PPCMCExpr::VK_PPC_HI;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HA:
|
|
Variant = PPCMCExpr::VK_PPC_HA;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HIGHER:
|
|
Variant = PPCMCExpr::VK_PPC_HIGHER;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HIGHERA:
|
|
Variant = PPCMCExpr::VK_PPC_HIGHERA;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HIGHEST:
|
|
Variant = PPCMCExpr::VK_PPC_HIGHEST;
|
|
break;
|
|
case MCSymbolRefExpr::VK_PPC_HIGHESTA:
|
|
Variant = PPCMCExpr::VK_PPC_HIGHESTA;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
|
|
}
|
|
|
|
case MCExpr::Unary: {
|
|
const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
|
|
const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
|
|
if (!Sub)
|
|
return 0;
|
|
return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
|
|
}
|
|
|
|
case MCExpr::Binary: {
|
|
const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
|
|
PPCMCExpr::VariantKind LHSVariant, RHSVariant;
|
|
const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
|
|
const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
|
|
|
|
if (!LHS && !RHS)
|
|
return 0;
|
|
|
|
if (!LHS) LHS = BE->getLHS();
|
|
if (!RHS) RHS = BE->getRHS();
|
|
|
|
if (LHSVariant == PPCMCExpr::VK_PPC_None)
|
|
Variant = RHSVariant;
|
|
else if (RHSVariant == PPCMCExpr::VK_PPC_None)
|
|
Variant = LHSVariant;
|
|
else if (LHSVariant == RHSVariant)
|
|
Variant = LHSVariant;
|
|
else
|
|
return 0;
|
|
|
|
return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Invalid expression kind!");
|
|
}
|
|
|
|
/// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
|
|
/// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
|
|
/// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
|
|
/// FIXME: This is a hack.
|
|
const MCExpr *PPCAsmParser::
|
|
FixupVariantKind(const MCExpr *E) {
|
|
MCContext &Context = getParser().getContext();
|
|
|
|
switch (E->getKind()) {
|
|
case MCExpr::Target:
|
|
case MCExpr::Constant:
|
|
return E;
|
|
|
|
case MCExpr::SymbolRef: {
|
|
const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
|
|
MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
|
|
|
|
switch (SRE->getKind()) {
|
|
case MCSymbolRefExpr::VK_TLSGD:
|
|
Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
|
|
break;
|
|
case MCSymbolRefExpr::VK_TLSLD:
|
|
Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
|
|
break;
|
|
default:
|
|
return E;
|
|
}
|
|
return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
|
|
}
|
|
|
|
case MCExpr::Unary: {
|
|
const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
|
|
const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
|
|
if (Sub == UE->getSubExpr())
|
|
return E;
|
|
return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
|
|
}
|
|
|
|
case MCExpr::Binary: {
|
|
const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
|
|
const MCExpr *LHS = FixupVariantKind(BE->getLHS());
|
|
const MCExpr *RHS = FixupVariantKind(BE->getRHS());
|
|
if (LHS == BE->getLHS() && RHS == BE->getRHS())
|
|
return E;
|
|
return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Invalid expression kind!");
|
|
}
|
|
|
|
/// ParseExpression. This differs from the default "parseExpression" in that
|
|
/// it handles modifiers.
|
|
bool PPCAsmParser::
|
|
ParseExpression(const MCExpr *&EVal) {
|
|
|
|
if (isDarwin())
|
|
return ParseDarwinExpression(EVal);
|
|
|
|
// (ELF Platforms)
|
|
// Handle \code @l/@ha \endcode
|
|
if (getParser().parseExpression(EVal))
|
|
return true;
|
|
|
|
EVal = FixupVariantKind(EVal);
|
|
|
|
PPCMCExpr::VariantKind Variant;
|
|
const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
|
|
if (E)
|
|
EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
|
|
|
|
return false;
|
|
}
|
|
|
|
/// ParseDarwinExpression. (MachO Platforms)
|
|
/// This differs from the default "parseExpression" in that it handles detection
|
|
/// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
|
|
/// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
|
|
/// syntax form so it is done here. TODO: Determine if there is merit in arranging
|
|
/// for this to be done at a higher level.
|
|
bool PPCAsmParser::
|
|
ParseDarwinExpression(const MCExpr *&EVal) {
|
|
PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
|
|
switch (getLexer().getKind()) {
|
|
default:
|
|
break;
|
|
case AsmToken::Identifier:
|
|
// Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
|
|
// something starting with any other char should be part of the
|
|
// asm syntax. If handwritten asm includes an identifier like lo16,
|
|
// then all bets are off - but no-one would do that, right?
|
|
StringRef poss = Parser.getTok().getString();
|
|
if (poss.equals_lower("lo16")) {
|
|
Variant = PPCMCExpr::VK_PPC_LO;
|
|
} else if (poss.equals_lower("hi16")) {
|
|
Variant = PPCMCExpr::VK_PPC_HI;
|
|
} else if (poss.equals_lower("ha16")) {
|
|
Variant = PPCMCExpr::VK_PPC_HA;
|
|
}
|
|
if (Variant != PPCMCExpr::VK_PPC_None) {
|
|
Parser.Lex(); // Eat the xx16
|
|
if (getLexer().isNot(AsmToken::LParen))
|
|
return Error(Parser.getTok().getLoc(), "expected '('");
|
|
Parser.Lex(); // Eat the '('
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (getParser().parseExpression(EVal))
|
|
return true;
|
|
|
|
if (Variant != PPCMCExpr::VK_PPC_None) {
|
|
if (getLexer().isNot(AsmToken::RParen))
|
|
return Error(Parser.getTok().getLoc(), "expected ')'");
|
|
Parser.Lex(); // Eat the ')'
|
|
EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// ParseOperand
|
|
/// This handles registers in the form 'NN', '%rNN' for ELF platforms and
|
|
/// rNN for MachO.
|
|
bool PPCAsmParser::
|
|
ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
SMLoc S = Parser.getTok().getLoc();
|
|
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
const MCExpr *EVal;
|
|
PPCOperand *Op;
|
|
|
|
// Attempt to parse the next token as an immediate
|
|
switch (getLexer().getKind()) {
|
|
// Special handling for register names. These are interpreted
|
|
// as immediates corresponding to the register number.
|
|
case AsmToken::Percent:
|
|
Parser.Lex(); // Eat the '%'.
|
|
unsigned RegNo;
|
|
int64_t IntVal;
|
|
if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
|
|
Parser.Lex(); // Eat the identifier token.
|
|
Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
|
|
Operands.push_back(Op);
|
|
return false;
|
|
}
|
|
return Error(S, "invalid register name");
|
|
|
|
case AsmToken::Identifier:
|
|
// Note that non-register-name identifiers from the compiler will begin
|
|
// with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
|
|
// identifiers like r31foo - so we fall through in the event that parsing
|
|
// a register name fails.
|
|
if (isDarwin()) {
|
|
unsigned RegNo;
|
|
int64_t IntVal;
|
|
if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
|
|
Parser.Lex(); // Eat the identifier token.
|
|
Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
|
|
Operands.push_back(Op);
|
|
return false;
|
|
}
|
|
}
|
|
// Fall-through to process non-register-name identifiers as expression.
|
|
// All other expressions
|
|
case AsmToken::LParen:
|
|
case AsmToken::Plus:
|
|
case AsmToken::Minus:
|
|
case AsmToken::Integer:
|
|
case AsmToken::Dot:
|
|
case AsmToken::Dollar:
|
|
case AsmToken::Exclaim:
|
|
case AsmToken::Tilde:
|
|
if (!ParseExpression(EVal))
|
|
break;
|
|
/* fall through */
|
|
default:
|
|
return Error(S, "unknown operand");
|
|
}
|
|
|
|
// Push the parsed operand into the list of operands
|
|
Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
|
|
Operands.push_back(Op);
|
|
|
|
// Check whether this is a TLS call expression
|
|
bool TLSCall = false;
|
|
if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
|
|
TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
|
|
|
|
if (TLSCall && getLexer().is(AsmToken::LParen)) {
|
|
const MCExpr *TLSSym;
|
|
|
|
Parser.Lex(); // Eat the '('.
|
|
S = Parser.getTok().getLoc();
|
|
if (ParseExpression(TLSSym))
|
|
return Error(S, "invalid TLS call expression");
|
|
if (getLexer().isNot(AsmToken::RParen))
|
|
return Error(Parser.getTok().getLoc(), "missing ')'");
|
|
E = Parser.getTok().getLoc();
|
|
Parser.Lex(); // Eat the ')'.
|
|
|
|
Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
|
|
Operands.push_back(Op);
|
|
}
|
|
|
|
// Otherwise, check for D-form memory operands
|
|
if (!TLSCall && getLexer().is(AsmToken::LParen)) {
|
|
Parser.Lex(); // Eat the '('.
|
|
S = Parser.getTok().getLoc();
|
|
|
|
int64_t IntVal;
|
|
switch (getLexer().getKind()) {
|
|
case AsmToken::Percent:
|
|
Parser.Lex(); // Eat the '%'.
|
|
unsigned RegNo;
|
|
if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
|
|
return Error(S, "invalid register name");
|
|
Parser.Lex(); // Eat the identifier token.
|
|
break;
|
|
|
|
case AsmToken::Integer:
|
|
if (!isDarwin()) {
|
|
if (getParser().parseAbsoluteExpression(IntVal) ||
|
|
IntVal < 0 || IntVal > 31)
|
|
return Error(S, "invalid register number");
|
|
} else {
|
|
return Error(S, "unexpected integer value");
|
|
}
|
|
break;
|
|
|
|
case AsmToken::Identifier:
|
|
if (isDarwin()) {
|
|
unsigned RegNo;
|
|
if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
|
|
Parser.Lex(); // Eat the identifier token.
|
|
break;
|
|
}
|
|
}
|
|
// Fall-through..
|
|
|
|
default:
|
|
return Error(S, "invalid memory operand");
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::RParen))
|
|
return Error(Parser.getTok().getLoc(), "missing ')'");
|
|
E = Parser.getTok().getLoc();
|
|
Parser.Lex(); // Eat the ')'.
|
|
|
|
Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
|
|
Operands.push_back(Op);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// Parse an instruction mnemonic followed by its operands.
|
|
bool PPCAsmParser::
|
|
ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
// The first operand is the token for the instruction name.
|
|
// If the next character is a '+' or '-', we need to add it to the
|
|
// instruction name, to match what TableGen is doing.
|
|
std::string NewOpcode;
|
|
if (getLexer().is(AsmToken::Plus)) {
|
|
getLexer().Lex();
|
|
NewOpcode = Name;
|
|
NewOpcode += '+';
|
|
Name = NewOpcode;
|
|
}
|
|
if (getLexer().is(AsmToken::Minus)) {
|
|
getLexer().Lex();
|
|
NewOpcode = Name;
|
|
NewOpcode += '-';
|
|
Name = NewOpcode;
|
|
}
|
|
// If the instruction ends in a '.', we need to create a separate
|
|
// token for it, to match what TableGen is doing.
|
|
size_t Dot = Name.find('.');
|
|
StringRef Mnemonic = Name.slice(0, Dot);
|
|
if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
|
|
Operands.push_back(
|
|
PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
|
|
else
|
|
Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
|
|
if (Dot != StringRef::npos) {
|
|
SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
|
|
StringRef DotStr = Name.slice(Dot, StringRef::npos);
|
|
if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
|
|
Operands.push_back(
|
|
PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
|
|
else
|
|
Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
|
|
}
|
|
|
|
// If there are no more operands then finish
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
return false;
|
|
|
|
// Parse the first operand
|
|
if (ParseOperand(Operands))
|
|
return true;
|
|
|
|
while (getLexer().isNot(AsmToken::EndOfStatement) &&
|
|
getLexer().is(AsmToken::Comma)) {
|
|
// Consume the comma token
|
|
getLexer().Lex();
|
|
|
|
// Parse the next operand
|
|
if (ParseOperand(Operands))
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirective parses the PPC specific directives
|
|
bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
|
|
StringRef IDVal = DirectiveID.getIdentifier();
|
|
if (!isDarwin()) {
|
|
if (IDVal == ".word")
|
|
return ParseDirectiveWord(2, DirectiveID.getLoc());
|
|
if (IDVal == ".llong")
|
|
return ParseDirectiveWord(8, DirectiveID.getLoc());
|
|
if (IDVal == ".tc")
|
|
return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
|
|
if (IDVal == ".machine")
|
|
return ParseDirectiveMachine(DirectiveID.getLoc());
|
|
} else {
|
|
if (IDVal == ".machine")
|
|
return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/// ParseDirectiveWord
|
|
/// ::= .word [ expression (, expression)* ]
|
|
bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
for (;;) {
|
|
const MCExpr *Value;
|
|
if (getParser().parseExpression(Value))
|
|
return false;
|
|
|
|
getParser().getStreamer().EmitValue(Value, Size);
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
break;
|
|
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveTC
|
|
/// ::= .tc [ symbol (, expression)* ]
|
|
bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
|
|
// Skip TC symbol, which is only used with XCOFF.
|
|
while (getLexer().isNot(AsmToken::EndOfStatement)
|
|
&& getLexer().isNot(AsmToken::Comma))
|
|
Parser.Lex();
|
|
if (getLexer().isNot(AsmToken::Comma)) {
|
|
Error(L, "unexpected token in directive");
|
|
return false;
|
|
}
|
|
Parser.Lex();
|
|
|
|
// Align to word size.
|
|
getParser().getStreamer().EmitValueToAlignment(Size);
|
|
|
|
// Emit expressions.
|
|
return ParseDirectiveWord(Size, L);
|
|
}
|
|
|
|
/// ParseDirectiveMachine (ELF platforms)
|
|
/// ::= .machine [ cpu | "push" | "pop" ]
|
|
bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::Identifier) &&
|
|
getLexer().isNot(AsmToken::String)) {
|
|
Error(L, "unexpected token in directive");
|
|
return false;
|
|
}
|
|
|
|
StringRef CPU = Parser.getTok().getIdentifier();
|
|
Parser.Lex();
|
|
|
|
// FIXME: Right now, the parser always allows any available
|
|
// instruction, so the .machine directive is not useful.
|
|
// Implement ".machine any" (by doing nothing) for the benefit
|
|
// of existing assembler code. Likewise, we can then implement
|
|
// ".machine push" and ".machine pop" as no-op.
|
|
if (CPU != "any" && CPU != "push" && CPU != "pop") {
|
|
Error(L, "unrecognized machine type");
|
|
return false;
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
Error(L, "unexpected token in directive");
|
|
return false;
|
|
}
|
|
PPCTargetStreamer &TStreamer =
|
|
*static_cast<PPCTargetStreamer *>(
|
|
getParser().getStreamer().getTargetStreamer());
|
|
TStreamer.emitMachine(CPU);
|
|
|
|
return false;
|
|
}
|
|
|
|
/// ParseDarwinDirectiveMachine (Mach-o platforms)
|
|
/// ::= .machine cpu-identifier
|
|
bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::Identifier) &&
|
|
getLexer().isNot(AsmToken::String)) {
|
|
Error(L, "unexpected token in directive");
|
|
return false;
|
|
}
|
|
|
|
StringRef CPU = Parser.getTok().getIdentifier();
|
|
Parser.Lex();
|
|
|
|
// FIXME: this is only the 'default' set of cpu variants.
|
|
// However we don't act on this information at present, this is simply
|
|
// allowing parsing to proceed with minimal sanity checking.
|
|
if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
|
|
Error(L, "unrecognized cpu type");
|
|
return false;
|
|
}
|
|
|
|
if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
|
|
Error(L, "wrong cpu type specified for 64bit");
|
|
return false;
|
|
}
|
|
if (!isPPC64() && CPU == "ppc64") {
|
|
Error(L, "wrong cpu type specified for 32bit");
|
|
return false;
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
Error(L, "unexpected token in directive");
|
|
return false;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// Force static initialization.
|
|
extern "C" void LLVMInitializePowerPCAsmParser() {
|
|
RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
|
|
RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
|
|
RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
|
|
}
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
#include "PPCGenAsmMatcher.inc"
|
|
|
|
// Define this matcher function after the auto-generated include so we
|
|
// have the match class enum definitions.
|
|
unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
|
|
unsigned Kind) {
|
|
// If the kind is a token for a literal immediate, check if our asm
|
|
// operand matches. This is for InstAliases which have a fixed-value
|
|
// immediate in the syntax.
|
|
int64_t ImmVal;
|
|
switch (Kind) {
|
|
case MCK_0: ImmVal = 0; break;
|
|
case MCK_1: ImmVal = 1; break;
|
|
case MCK_2: ImmVal = 2; break;
|
|
case MCK_3: ImmVal = 3; break;
|
|
default: return Match_InvalidOperand;
|
|
}
|
|
|
|
PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
|
|
if (Op->isImm() && Op->getImm() == ImmVal)
|
|
return Match_Success;
|
|
|
|
return Match_InvalidOperand;
|
|
}
|
|
|
|
const MCExpr *
|
|
PPCAsmParser::applyModifierToExpr(const MCExpr *E,
|
|
MCSymbolRefExpr::VariantKind Variant,
|
|
MCContext &Ctx) {
|
|
switch (Variant) {
|
|
case MCSymbolRefExpr::VK_PPC_LO:
|
|
return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
|
|
case MCSymbolRefExpr::VK_PPC_HI:
|
|
return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
|
|
case MCSymbolRefExpr::VK_PPC_HA:
|
|
return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
|
|
case MCSymbolRefExpr::VK_PPC_HIGHER:
|
|
return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
|
|
case MCSymbolRefExpr::VK_PPC_HIGHERA:
|
|
return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
|
|
case MCSymbolRefExpr::VK_PPC_HIGHEST:
|
|
return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
|
|
case MCSymbolRefExpr::VK_PPC_HIGHESTA:
|
|
return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|