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2363b4ef5b
functions for now). This automatically turns on the printing of machine registers using their own real names, instead of goofy things like %mreg(42), and allows us to migrate code incrementally to the new interface as we see fit. The register file description it uses is hand-written, so that the register numbers will match the ones that the SparcV9 target already uses. Perhaps someday we'll tablegen it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13145 91177308-0d34-0410-b5e6-96231b3b80d8
313 lines
11 KiB
C++
313 lines
11 KiB
C++
//===- SparcV9RegisterInfo.cpp - SparcV9 Register Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV9 implementation of the MRegisterInfo class.
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// It also contains stuff needed to instantiate that class, which would
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// ordinarily be provided by TableGen.
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//
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// This is NOT used by the SparcV9 backend to do register allocation, yet.
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//
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//===----------------------------------------------------------------------===//
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//
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// The first section of this file (immediately following) is what
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// you would find in SparcV9GenRegisterInfo.inc, if we were using
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// TableGen to generate the register file description automatically.
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// It consists of register classes and register class instances
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// for the SparcV9 target.
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//
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// FIXME: the alignments listed here are wild guesses.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV9RegisterInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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using namespace llvm;
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namespace llvm {
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namespace {
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// IR Register Class...
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const unsigned IR[] = {
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SparcV9::o0, SparcV9::o1, SparcV9::o2, SparcV9::o3, SparcV9::o4,
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SparcV9::o5, SparcV9::o7, SparcV9::l0, SparcV9::l1, SparcV9::l2,
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SparcV9::l3, SparcV9::l4, SparcV9::l5, SparcV9::l6, SparcV9::l7,
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SparcV9::i0, SparcV9::i1, SparcV9::i2, SparcV9::i3, SparcV9::i4,
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SparcV9::i5, SparcV9::i6, SparcV9::i7, SparcV9::g0, SparcV9::g1,
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SparcV9::g2, SparcV9::g3, SparcV9::g4, SparcV9::g5, SparcV9::g6,
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SparcV9::g7, SparcV9::o6
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};
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struct IRClass : public TargetRegisterClass {
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IRClass() : TargetRegisterClass(8, 8, IR, IR + 32) {}
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} IRInstance;
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// FR Register Class...
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const unsigned FR[] = {
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SparcV9::f0, SparcV9::f1, SparcV9::f2, SparcV9::f3, SparcV9::f4,
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SparcV9::f5, SparcV9::f6, SparcV9::f7, SparcV9::f8, SparcV9::f9,
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SparcV9::f10, SparcV9::f11, SparcV9::f12, SparcV9::f13,
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SparcV9::f14, SparcV9::f15, SparcV9::f16, SparcV9::f17,
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SparcV9::f18, SparcV9::f19, SparcV9::f20, SparcV9::f21,
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SparcV9::f22, SparcV9::f23, SparcV9::f24, SparcV9::f25,
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SparcV9::f26, SparcV9::f27, SparcV9::f28, SparcV9::f29,
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SparcV9::f30, SparcV9::f31, SparcV9::f32, SparcV9::f33,
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SparcV9::f34, SparcV9::f35, SparcV9::f36, SparcV9::f37,
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SparcV9::f38, SparcV9::f39, SparcV9::f40, SparcV9::f41,
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SparcV9::f42, SparcV9::f43, SparcV9::f44, SparcV9::f45,
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SparcV9::f46, SparcV9::f47, SparcV9::f48, SparcV9::f49,
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SparcV9::f50, SparcV9::f51, SparcV9::f52, SparcV9::f53,
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SparcV9::f54, SparcV9::f55, SparcV9::f56, SparcV9::f57,
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SparcV9::f58, SparcV9::f59, SparcV9::f60, SparcV9::f61,
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SparcV9::f62, SparcV9::f63
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};
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// FIXME: The size is correct for the first 32 registers. The
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// latter 32 do not all really exist; you can only access every other
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// one (32, 34, ...), and they must contain double-fp or quad-fp
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// values... see below about the aliasing problems.
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struct FRClass : public TargetRegisterClass {
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FRClass() : TargetRegisterClass(4, 8, FR, FR + 64) {}
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} FRInstance;
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// ICCR Register Class...
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const unsigned ICCR[] = {
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SparcV9::xcc, SparcV9::icc, SparcV9::ccr
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};
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struct ICCRClass : public TargetRegisterClass {
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ICCRClass() : TargetRegisterClass(1, 8, ICCR, ICCR + 3) {}
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} ICCRInstance;
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// FCCR Register Class...
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const unsigned FCCR[] = {
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SparcV9::fcc0, SparcV9::fcc1, SparcV9::fcc2, SparcV9::fcc3
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};
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struct FCCRClass : public TargetRegisterClass {
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FCCRClass() : TargetRegisterClass(1, 8, FCCR, FCCR + 4) {}
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} FCCRInstance;
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// SR Register Class...
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const unsigned SR[] = {
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SparcV9::fsr
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};
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struct SRClass : public TargetRegisterClass {
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SRClass() : TargetRegisterClass(8, 8, SR, SR + 1) {}
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} SRInstance;
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// Register Classes...
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const TargetRegisterClass* const RegisterClasses[] = {
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&IRInstance,
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&FRInstance,
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&ICCRInstance,
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&FCCRInstance,
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&SRInstance
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};
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// Register Alias Sets...
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// FIXME: Note that the SparcV9 backend does not currently abstract
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// very well over the way that double-fp and quad-fp values may alias
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// single-fp values in registers. Therefore those aliases are NOT
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// reflected here.
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const unsigned Empty_AliasSet[] = { 0 };
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const unsigned fcc3_AliasSet[] = { SparcV9::fsr, 0 };
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const unsigned fcc2_AliasSet[] = { SparcV9::fsr, 0 };
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const unsigned fcc1_AliasSet[] = { SparcV9::fsr, 0 };
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const unsigned fcc0_AliasSet[] = { SparcV9::fsr, 0 };
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const unsigned fsr_AliasSet[] = { SparcV9::fcc3, SparcV9::fcc2,
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SparcV9::fcc1, SparcV9::fcc0, 0 };
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const unsigned xcc_AliasSet[] = { SparcV9::ccr, 0 };
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const unsigned icc_AliasSet[] = { SparcV9::ccr, 0 };
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const unsigned ccr_AliasSet[] = { SparcV9::xcc, SparcV9::icc, 0 };
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const MRegisterDesc RegisterDescriptors[] = { // Descriptors
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{ "o0", Empty_AliasSet, 0, 0 },
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{ "o1", Empty_AliasSet, 0, 0 },
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{ "o2", Empty_AliasSet, 0, 0 },
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{ "o3", Empty_AliasSet, 0, 0 },
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{ "o4", Empty_AliasSet, 0, 0 },
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{ "o5", Empty_AliasSet, 0, 0 },
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{ "o7", Empty_AliasSet, 0, 0 },
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{ "l0", Empty_AliasSet, 0, 0 },
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{ "l1", Empty_AliasSet, 0, 0 },
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{ "l2", Empty_AliasSet, 0, 0 },
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{ "l3", Empty_AliasSet, 0, 0 },
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{ "l4", Empty_AliasSet, 0, 0 },
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{ "l5", Empty_AliasSet, 0, 0 },
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{ "l6", Empty_AliasSet, 0, 0 },
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{ "l7", Empty_AliasSet, 0, 0 },
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{ "i0", Empty_AliasSet, 0, 0 },
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{ "i1", Empty_AliasSet, 0, 0 },
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{ "i2", Empty_AliasSet, 0, 0 },
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{ "i3", Empty_AliasSet, 0, 0 },
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{ "i4", Empty_AliasSet, 0, 0 },
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{ "i5", Empty_AliasSet, 0, 0 },
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{ "i6", Empty_AliasSet, 0, 0 },
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{ "i7", Empty_AliasSet, 0, 0 },
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{ "g0", Empty_AliasSet, 0, 0 },
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{ "g1", Empty_AliasSet, 0, 0 },
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{ "g2", Empty_AliasSet, 0, 0 },
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{ "g3", Empty_AliasSet, 0, 0 },
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{ "g4", Empty_AliasSet, 0, 0 },
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{ "g5", Empty_AliasSet, 0, 0 },
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{ "g6", Empty_AliasSet, 0, 0 },
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{ "g7", Empty_AliasSet, 0, 0 },
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{ "o6", Empty_AliasSet, 0, 0 },
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{ "f0", Empty_AliasSet, 0, 0 },
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{ "f1", Empty_AliasSet, 0, 0 },
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{ "f2", Empty_AliasSet, 0, 0 },
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{ "f3", Empty_AliasSet, 0, 0 },
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{ "f4", Empty_AliasSet, 0, 0 },
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{ "f5", Empty_AliasSet, 0, 0 },
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{ "f6", Empty_AliasSet, 0, 0 },
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{ "f7", Empty_AliasSet, 0, 0 },
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{ "f8", Empty_AliasSet, 0, 0 },
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{ "f9", Empty_AliasSet, 0, 0 },
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{ "f10", Empty_AliasSet, 0, 0 },
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{ "f11", Empty_AliasSet, 0, 0 },
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{ "f12", Empty_AliasSet, 0, 0 },
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{ "f13", Empty_AliasSet, 0, 0 },
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{ "f14", Empty_AliasSet, 0, 0 },
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{ "f15", Empty_AliasSet, 0, 0 },
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{ "f16", Empty_AliasSet, 0, 0 },
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{ "f17", Empty_AliasSet, 0, 0 },
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{ "f18", Empty_AliasSet, 0, 0 },
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{ "f19", Empty_AliasSet, 0, 0 },
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{ "f20", Empty_AliasSet, 0, 0 },
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{ "f21", Empty_AliasSet, 0, 0 },
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{ "f22", Empty_AliasSet, 0, 0 },
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{ "f23", Empty_AliasSet, 0, 0 },
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{ "f24", Empty_AliasSet, 0, 0 },
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{ "f25", Empty_AliasSet, 0, 0 },
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{ "f26", Empty_AliasSet, 0, 0 },
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{ "f27", Empty_AliasSet, 0, 0 },
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{ "f28", Empty_AliasSet, 0, 0 },
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{ "f29", Empty_AliasSet, 0, 0 },
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{ "f30", Empty_AliasSet, 0, 0 },
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{ "f31", Empty_AliasSet, 0, 0 },
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{ "f32", Empty_AliasSet, 0, 0 },
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{ "f33", Empty_AliasSet, 0, 0 },
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{ "f34", Empty_AliasSet, 0, 0 },
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{ "f35", Empty_AliasSet, 0, 0 },
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{ "f36", Empty_AliasSet, 0, 0 },
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{ "f37", Empty_AliasSet, 0, 0 },
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{ "f38", Empty_AliasSet, 0, 0 },
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{ "f39", Empty_AliasSet, 0, 0 },
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{ "f40", Empty_AliasSet, 0, 0 },
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{ "f41", Empty_AliasSet, 0, 0 },
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{ "f42", Empty_AliasSet, 0, 0 },
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{ "f43", Empty_AliasSet, 0, 0 },
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{ "f44", Empty_AliasSet, 0, 0 },
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{ "f45", Empty_AliasSet, 0, 0 },
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{ "f46", Empty_AliasSet, 0, 0 },
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{ "f47", Empty_AliasSet, 0, 0 },
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{ "f48", Empty_AliasSet, 0, 0 },
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{ "f49", Empty_AliasSet, 0, 0 },
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{ "f50", Empty_AliasSet, 0, 0 },
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{ "f51", Empty_AliasSet, 0, 0 },
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{ "f52", Empty_AliasSet, 0, 0 },
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{ "f53", Empty_AliasSet, 0, 0 },
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{ "f54", Empty_AliasSet, 0, 0 },
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{ "f55", Empty_AliasSet, 0, 0 },
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{ "f56", Empty_AliasSet, 0, 0 },
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{ "f57", Empty_AliasSet, 0, 0 },
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{ "f58", Empty_AliasSet, 0, 0 },
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{ "f59", Empty_AliasSet, 0, 0 },
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{ "f60", Empty_AliasSet, 0, 0 },
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{ "f61", Empty_AliasSet, 0, 0 },
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{ "f62", Empty_AliasSet, 0, 0 },
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{ "f63", Empty_AliasSet, 0, 0 },
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{ "xcc", xcc_AliasSet, 0, 0 },
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{ "icc", icc_AliasSet, 0, 0 },
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{ "ccr", ccr_AliasSet, 0, 0 },
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{ "fcc0", fcc0_AliasSet, 0, 0 },
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{ "fcc1", fcc1_AliasSet, 0, 0 },
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{ "fcc2", fcc2_AliasSet, 0, 0 },
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{ "fcc3", fcc3_AliasSet, 0, 0 },
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{ "fsr", fsr_AliasSet, 0, 0 },
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};
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} // end anonymous namespace
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namespace SparcV9 { // Register classes
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TargetRegisterClass *IRRegisterClass = &IRInstance;
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TargetRegisterClass *FRRegisterClass = &FRInstance;
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TargetRegisterClass *ICCRRegisterClass = &ICCRInstance;
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TargetRegisterClass *FCCRRegisterClass = &FCCRInstance;
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TargetRegisterClass *SRRegisterClass = &SRInstance;
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} // end namespace SparcV9
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const unsigned *SparcV9RegisterInfo::getCalleeSaveRegs() const {
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// FIXME: This should be verified against the SparcV9 ABI at some point.
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// These are the registers which the SparcV9 backend considers
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// "non-volatile".
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static const unsigned CalleeSaveRegs[] = {
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SparcV9::l0, SparcV9::l1, SparcV9::l2, SparcV9::l3, SparcV9::l4,
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SparcV9::l5, SparcV9::l6, SparcV9::l7, SparcV9::i0, SparcV9::i1,
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SparcV9::i2, SparcV9::i3, SparcV9::i4, SparcV9::i5, SparcV9::i6,
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SparcV9::i7, SparcV9::g0, SparcV9::g1, SparcV9::g2, SparcV9::g3,
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SparcV9::g4, SparcV9::g5, SparcV9::g6, SparcV9::g7, SparcV9::o6,
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0
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};
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return CalleeSaveRegs;
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}
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} // end namespace llvm
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//===----------------------------------------------------------------------===//
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//
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// The second section of this file (immediately following) contains the
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// SparcV9 implementation of the MRegisterInfo class. It currently consists
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// entirely of stub functions, because the SparcV9 target does not use the
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// same register allocator that the X86 target uses.
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//
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//===----------------------------------------------------------------------===//
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SparcV9RegisterInfo::SparcV9RegisterInfo ()
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: MRegisterInfo (RegisterDescriptors, 104, RegisterClasses,
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RegisterClasses + 5) {
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}
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int SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIndex,
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const TargetRegisterClass *RC) const {
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abort ();
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}
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int SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const {
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abort ();
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}
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int SparcV9RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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abort ();
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}
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void SparcV9RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
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MachineBasicBlock::iterator MI) const {
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abort ();
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}
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void SparcV9RegisterInfo::emitPrologue(MachineFunction &MF) const {
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abort ();
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}
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void SparcV9RegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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abort ();
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}
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