mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
2.8 KiB
LLVM
63 lines
2.8 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=SI %s
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; RUN: llc < %s -march=r600 -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=CI %s
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@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] zeroinitializer, align 4
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@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] zeroinitializer, align 4
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; EG-CHECK: {{^}}local_memory_two_objects:
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; Check that the LDS size emitted correctly
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; EG-CHECK: .long 166120
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; EG-CHECK-NEXT: .long 8
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; SI-CHECK: .long 47180
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; SI-CHECK-NEXT: .long 32768
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; We would like to check the the lds writes are using different
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; addresses, but due to variations in the scheduler, we can't do
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; this consistently on evergreen GPUs.
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; EG-CHECK: LDS_WRITE
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; EG-CHECK: LDS_WRITE
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; SI-CHECK: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
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; SI-CHECK-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]]
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; GROUP_BARRIER must be the last instruction in a clause
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; EG-CHECK: GROUP_BARRIER
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; EG-CHECK-NEXT: ALU clause
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; Make sure the lds reads are using different addresses, at different
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; constant offsets.
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; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
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; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
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; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}}
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; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] [M0]
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; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16 [M0]
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; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] [M0]
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define void @local_memory_two_objects(i32 addrspace(1)* %out) {
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entry:
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%x.i = call i32 @llvm.r600.read.tidig.x() #0
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%arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
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store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
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%mul = shl nsw i32 %x.i, 1
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%arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
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store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
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%sub = sub nsw i32 3, %x.i
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call void @llvm.AMDGPU.barrier.local()
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%arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
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%0 = load i32 addrspace(3)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i
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store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
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%1 = load i32 addrspace(3)* %arrayidx4, align 4
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%add = add nsw i32 %x.i, 4
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%arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add
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store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #0
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declare void @llvm.AMDGPU.barrier.local()
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attributes #0 = { readnone }
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