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https://github.com/c64scene-ar/llvm-6502.git
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556578ec0c
cases from Halide folks. This initial step was extracted from a prototype change by Clay Wood to try and address regressions found with Halide and the new vector shuffle lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221779 91177308-0d34-0410-b5e6-96231b3b80d8
207 lines
8.1 KiB
LLVM
207 lines
8.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
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; SSE2-LABEL: zext_8i16_to_8i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movdqa %xmm0, %xmm2
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
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; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
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; SSE2-NEXT: pand %xmm1, %xmm2
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; SSE2-NEXT: pand %xmm0, %xmm1
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; SSE2-NEXT: movdqa %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: zext_8i16_to_8i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movdqa %xmm0, %xmm2
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
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; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
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; SSSE3-NEXT: pand %xmm1, %xmm2
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; SSSE3-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; SSSE3-NEXT: pand %xmm0, %xmm1
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; SSSE3-NEXT: movdqa %xmm2, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: zext_8i16_to_8i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovzxwd %xmm0, %xmm2
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; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
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; SSE41-NEXT: pand %xmm1, %xmm2
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; SSE41-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; SSE41-NEXT: pand %xmm0, %xmm1
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: zext_8i16_to_8i32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
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; AVX1-NEXT: vpmovzxwd %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: zext_8i16_to_8i32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpmovzxwd %xmm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%B = zext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
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; SSE2-LABEL: zext_4i32_to_4i64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
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; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
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; SSE2-NEXT: pand %xmm3, %xmm2
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
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; SSE2-NEXT: pand %xmm3, %xmm1
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; SSE2-NEXT: movdqa %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: zext_4i32_to_4i64:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
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; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
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; SSSE3-NEXT: pand %xmm3, %xmm2
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
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; SSSE3-NEXT: pand %xmm3, %xmm1
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; SSSE3-NEXT: movdqa %xmm2, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: zext_4i32_to_4i64:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovzxdq %xmm0, %xmm2
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; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
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; SSE41-NEXT: pand %xmm3, %xmm2
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; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
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; SSE41-NEXT: pand %xmm3, %xmm1
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: zext_4i32_to_4i64:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; AVX1-NEXT: vpmovzxdq %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: zext_4i32_to_4i64:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpmovzxdq %xmm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%B = zext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
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; SSE2-LABEL: zext_8i8_to_8i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movdqa %xmm0, %xmm2
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
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; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255]
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; SSE2-NEXT: pand %xmm1, %xmm2
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; SSE2-NEXT: pand %xmm0, %xmm1
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; SSE2-NEXT: movdqa %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: zext_8i8_to_8i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movdqa %xmm0, %xmm2
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
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; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255]
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; SSSE3-NEXT: pand %xmm1, %xmm2
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; SSSE3-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; SSSE3-NEXT: pand %xmm0, %xmm1
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; SSSE3-NEXT: movdqa %xmm2, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: zext_8i8_to_8i32:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovzxwd %xmm0, %xmm2
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; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255]
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; SSE41-NEXT: pand %xmm1, %xmm2
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; SSE41-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; SSE41-NEXT: pand %xmm0, %xmm1
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: zext_8i8_to_8i32:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpmovzxwd %xmm0, %xmm1
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; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: zext_8i8_to_8i32:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpmovzxwd %xmm0, %ymm0
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; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%t = zext <8 x i8> %z to <8 x i32>
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ret <8 x i32> %t
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}
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; PR17654
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define <16 x i16> @zext_16i8_to_16i16(<16 x i8> %z) {
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; SSE2-LABEL: zext_16i8_to_16i16:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movdqa %xmm0, %xmm2
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
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; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
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; SSE2-NEXT: pand %xmm1, %xmm2
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; SSE2-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
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; SSE2-NEXT: pand %xmm0, %xmm1
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; SSE2-NEXT: movdqa %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: zext_16i8_to_16i16:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movdqa %xmm0, %xmm2
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
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; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
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; SSSE3-NEXT: pand %xmm1, %xmm2
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; SSSE3-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
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; SSSE3-NEXT: pand %xmm0, %xmm1
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; SSSE3-NEXT: movdqa %xmm2, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: zext_16i8_to_16i16:
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; SSE41: # BB#0: # %entry
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; SSE41-NEXT: pmovzxbw %xmm0, %xmm2
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; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
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; SSE41-NEXT: pand %xmm1, %xmm2
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; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
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; SSE41-NEXT: pand %xmm0, %xmm1
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; SSE41-NEXT: movdqa %xmm2, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: zext_16i8_to_16i16:
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; AVX1: # BB#0: # %entry
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
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; AVX1-NEXT: vpmovzxbw %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: zext_16i8_to_16i16:
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; AVX2: # BB#0: # %entry
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; AVX2-NEXT: vpmovzxbw %xmm0, %ymm0
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; AVX2-NEXT: retq
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entry:
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%t = zext <16 x i8> %z to <16 x i16>
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ret <16 x i16> %t
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}
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