llvm-6502/test/CodeGen
2013-01-05 07:39:25 +00:00
..
ARM
CPP
Generic
Hexagon
MBlaze
Mips [mips] MipsTargetLowering::getSetCCResultType should return a vector type if 2013-01-04 20:06:01 +00:00
MSP430
NVPTX
PowerPC Support ppcf128 in SelectionDAG::getConstantFP 2012-12-30 19:03:32 +00:00
R600 DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes 2013-01-02 22:13:01 +00:00
SI
SPARC
Thumb
Thumb2
X86 Recommit r171461 which was incorrectly reverted. Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks. 2013-01-05 07:39:25 +00:00
XCore