Elena Demikhovsky 52981c4b60 I optimized the following patterns: ... sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-20 12:42:54 +00:00
..
BasicAA	Modify the LLVM assembly output so that it uses references to represent function attributes.	2013-02-20 07:21:42 +00:00
BlockFrequencyInfo
BranchProbabilityInfo
CallGraph	Now that invoke of an intrinsic is possible (for the llvm.do.nothing intrinsic)	2012-09-26 17:16:01 +00:00
CostModel	I optimized the following patterns:	2013-02-20 12:42:54 +00:00
DependenceAnalysis	Modified dump() to provide a little	2012-11-30 00:44:47 +00:00
Dominators	Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID	2012-12-30 02:33:22 +00:00
GlobalsModRef
LoopInfo
PostDominators
Profiling	AArch64: adjust tests which rely on a default JIT	2013-02-18 11:08:37 +00:00
RegionInfo	Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID	2012-12-30 02:33:22 +00:00
ScalarEvolution	Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID	2012-12-30 02:33:22 +00:00
TypeBasedAliasAnalysis	Modify the LLVM assembly output so that it uses references to represent function attributes.	2013-02-20 07:21:42 +00:00