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TargetMachine.cpp, since it is entirely machine-independent. Also, add options to disable optional back-end passes (preselection and instr. scheduling). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3740 91177308-0d34-0410-b5e6-96231b3b80d8
233 lines
7.3 KiB
C++
233 lines
7.3 KiB
C++
//===-- TargetMachine.cpp - General Target Information ---------------------==//
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//
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// This file describes the general parts of a Target machine.
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// This file also implements MachineInstrInfo and MachineCacheInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/MachineCacheInfo.h"
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#include "llvm/CodeGen/PreSelection.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/RegisterAllocation.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/Reoptimizer/Mapping/MappingInfo.h"
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#include "llvm/Reoptimizer/Mapping/FInfo.h"
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#include "llvm/Transforms/Scalar.h"
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#include "Support/CommandLine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Function.h"
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#include "llvm/DerivedTypes.h"
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//---------------------------------------------------------------------------
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// Command line options to control choice of code generation passes.
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//---------------------------------------------------------------------------
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static cl::opt<bool> DisablePreSelect("nopreselect",
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cl::desc("Disable preselection pass"));
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static cl::opt<bool> DisableSched("nosched",
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cl::desc("Disable local scheduling pass"));
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//---------------------------------------------------------------------------
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// class TargetMachine
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//
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// Purpose:
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// Machine description.
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//
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//---------------------------------------------------------------------------
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// function TargetMachine::findOptimalStorageSize
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//
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// Purpose:
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// This default implementation assumes that all sub-word data items use
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// space equal to optSizeForSubWordData, and all other primitive data
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// items use space according to the type.
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//
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unsigned int
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TargetMachine::findOptimalStorageSize(const Type* ty) const
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{
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switch(ty->getPrimitiveID())
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{
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case Type::BoolTyID:
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case Type::UByteTyID:
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case Type::SByteTyID:
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case Type::UShortTyID:
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case Type::ShortTyID:
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return optSizeForSubWordData;
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default:
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return DataLayout.getTypeSize(ty);
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}
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}
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//===---------------------------------------------------------------------===//
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// Default code generation passes.
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//
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// Native code generation for a specified target.
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//===---------------------------------------------------------------------===//
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class ConstructMachineCodeForFunction : public FunctionPass {
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TargetMachine &Target;
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public:
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inline ConstructMachineCodeForFunction(TargetMachine &T) : Target(T) {}
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const char *getPassName() const {
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return "ConstructMachineCodeForFunction";
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}
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bool runOnFunction(Function &F) {
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MachineCodeForMethod::construct(&F, Target);
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return false;
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}
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};
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struct FreeMachineCodeForFunction : public FunctionPass {
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const char *getPassName() const { return "FreeMachineCodeForFunction"; }
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static void freeMachineCode(Instruction &I) {
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MachineCodeForInstruction::destroy(&I);
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}
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bool runOnFunction(Function &F) {
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
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MachineCodeForInstruction::get(I).dropAllReferences();
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for_each(FI->begin(), FI->end(), freeMachineCode);
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return false;
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}
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};
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// addPassesToEmitAssembly - This method controls the entire code generation
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// process for the ultra sparc.
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//
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void
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TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
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{
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// Construct and initialize the MachineCodeForMethod object for this fn.
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PM.add(new ConstructMachineCodeForFunction(*this));
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// Specialize LLVM code for this target machine and then
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// run basic dataflow optimizations on LLVM code.
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if (!DisablePreSelect)
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{
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PM.add(createPreSelectionPass(*this));
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PM.add(createReassociatePass());
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PM.add(createGCSEPass());
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PM.add(createLICMPass());
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}
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PM.add(createInstructionSelectionPass(*this));
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if (!DisableSched)
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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PM.add(getRegisterAllocator(*this));
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//PM.add(new OptimizeLeafProcedures());
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//PM.add(new DeleteFallThroughBranches());
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//PM.add(new RemoveChainedBranches()); // should be folded with previous
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//PM.add(new RemoveRedundantOps()); // operations with %g0, NOP, etc.
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PM.add(getPrologEpilogInsertionPass());
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PM.add(MappingInfoForFunction(Out));
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// Output assembly language to the .s file. Assembly emission is split into
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// two parts: Function output and Global value output. This is because
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// function output is pipelined with all of the rest of code generation stuff,
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// allowing machine code representations for functions to be free'd after the
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// function has been emitted.
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//
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PM.add(getFunctionAsmPrinterPass(Out));
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PM.add(new FreeMachineCodeForFunction()); // Free stuff no longer needed
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// Emit Module level assembly after all of the functions have been processed.
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PM.add(getModuleAsmPrinterPass(Out));
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// Emit bytecode to the assembly file into its special section next
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PM.add(getEmitBytecodeToAsmPass(Out));
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PM.add(getFunctionInfo(Out));
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}
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//---------------------------------------------------------------------------
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// class MachineInstructionInfo
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// Interface to description of machine instructions
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//---------------------------------------------------------------------------
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/*ctor*/
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MachineInstrInfo::MachineInstrInfo(const TargetMachine& tgt,
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const MachineInstrDescriptor* _desc,
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unsigned int _descSize,
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unsigned int _numRealOpCodes)
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: target(tgt),
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desc(_desc), descSize(_descSize), numRealOpCodes(_numRealOpCodes)
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{
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// FIXME: TargetInstrDescriptors should not be global
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assert(TargetInstrDescriptors == NULL && desc != NULL);
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TargetInstrDescriptors = desc; // initialize global variable
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}
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MachineInstrInfo::~MachineInstrInfo()
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{
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TargetInstrDescriptors = NULL; // reset global variable
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}
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bool
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MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
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int64_t intValue) const
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{
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// First, check if opCode has an immed field.
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bool isSignExtended;
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uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
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if (maxImmedValue != 0)
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{
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// NEED TO HANDLE UNSIGNED VALUES SINCE THEY MAY BECOME MUCH
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// SMALLER AFTER CASTING TO SIGN-EXTENDED int, short, or char.
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// See CreateUIntSetInstruction in SparcInstrInfo.cpp.
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// Now check if the constant fits
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if (intValue <= (int64_t) maxImmedValue &&
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intValue >= -((int64_t) maxImmedValue+1))
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return true;
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}
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return false;
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}
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//---------------------------------------------------------------------------
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// class MachineCacheInfo
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//
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// Purpose:
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// Describes properties of the target cache architecture.
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//---------------------------------------------------------------------------
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/*ctor*/
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MachineCacheInfo::MachineCacheInfo(const TargetMachine& tgt)
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: target(tgt)
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{
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Initialize();
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}
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void
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MachineCacheInfo::Initialize()
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{
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numLevels = 2;
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cacheLineSizes.push_back(16); cacheLineSizes.push_back(32);
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cacheSizes.push_back(1 << 15); cacheSizes.push_back(1 << 20);
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cacheAssoc.push_back(1); cacheAssoc.push_back(4);
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}
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