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https://github.com/c64scene-ar/llvm-6502.git
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04ee5a1d92
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
503 lines
17 KiB
C++
503 lines
17 KiB
C++
//===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the XCore implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreMachineFunctionInfo.h"
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#include "XCoreInstrInfo.h"
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#include "XCore.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "XCoreGenInstrInfo.inc"
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#include "llvm/Support/Debug.h"
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namespace llvm {
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namespace XCore {
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// XCore Condition Codes
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enum CondCode {
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COND_TRUE,
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COND_FALSE,
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COND_INVALID
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};
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}
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}
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using namespace llvm;
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XCoreInstrInfo::XCoreInstrInfo(void)
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: TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)),
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RI(*this) {
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}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSR, unsigned &DstSR) const {
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SrcSR = DstSR = 0; // No sub-registers.
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// We look for 4 kinds of patterns here:
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// add dst, src, 0
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// sub dst, src, 0
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// or dst, src, src
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// and dst, src, src
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if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus)
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&& isZeroImm(MI.getOperand(2))) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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} else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r)
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&& MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned
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XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
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int Opcode = MI->getOpcode();
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if (Opcode == XCore::LDWFI)
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{
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2))))
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{
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned
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XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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int Opcode = MI->getOpcode();
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if (Opcode == XCore::STWFI)
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{
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2))))
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{
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isInvariantLoad - Return true if the specified instruction (which is marked
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/// mayLoad) is loading from a location whose value is invariant across the
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/// function. For example, loading a value from the constant pool or from
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/// from the argument area of a function if it does not change. This should
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/// only return true of *all* loads the instruction does are invariant (if it
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/// does multiple loads).
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bool
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XCoreInstrInfo::isInvariantLoad(const MachineInstr *MI) const {
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// Loads from constants pools and loads from invariant argument slots are
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// invariant
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int Opcode = MI->getOpcode();
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if (Opcode == XCore::LDWCP_ru6 || Opcode == XCore::LDWCP_lru6) {
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return MI->getOperand(1).isCPI();
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}
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int FrameIndex;
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if (isLoadFromStackSlot(MI, FrameIndex)) {
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const MachineFrameInfo &MFI =
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*MI->getParent()->getParent()->getFrameInfo();
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return MFI.isFixedObjectIndex(FrameIndex) &&
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MFI.isImmutableObjectIndex(FrameIndex);
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}
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return false;
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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static inline bool IsBRU(unsigned BrOpc) {
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return BrOpc == XCore::BRFU_u6
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|| BrOpc == XCore::BRFU_lu6
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|| BrOpc == XCore::BRBU_u6
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|| BrOpc == XCore::BRBU_lu6;
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}
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static inline bool IsBRT(unsigned BrOpc) {
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return BrOpc == XCore::BRFT_ru6
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|| BrOpc == XCore::BRFT_lru6
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|| BrOpc == XCore::BRBT_ru6
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|| BrOpc == XCore::BRBT_lru6;
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}
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static inline bool IsBRF(unsigned BrOpc) {
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return BrOpc == XCore::BRFF_ru6
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|| BrOpc == XCore::BRFF_lru6
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|| BrOpc == XCore::BRBF_ru6
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|| BrOpc == XCore::BRBF_lru6;
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}
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static inline bool IsCondBranch(unsigned BrOpc) {
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return IsBRF(BrOpc) || IsBRT(BrOpc);
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}
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/// GetCondFromBranchOpc - Return the XCore CC that matches
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/// the correspondent Branch instruction opcode.
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static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
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{
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if (IsBRT(BrOpc)) {
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return XCore::COND_TRUE;
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} else if (IsBRF(BrOpc)) {
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return XCore::COND_FALSE;
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} else {
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return XCore::COND_INVALID;
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}
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}
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/// GetCondBranchFromCond - Return the Branch instruction
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/// opcode that matches the cc.
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static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
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{
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switch (CC) {
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default: assert(0 && "Illegal condition code!");
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case XCore::COND_TRUE : return XCore::BRFT_lru6;
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case XCore::COND_FALSE : return XCore::BRFF_lru6;
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}
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}
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/// GetOppositeBranchCondition - Return the inverse of the specified
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/// condition, e.g. turning COND_E to COND_NE.
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static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
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{
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switch (CC) {
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default: assert(0 && "Illegal condition code!");
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case XCore::COND_TRUE : return XCore::COND_FALSE;
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case XCore::COND_FALSE : return XCore::COND_TRUE;
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}
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}
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/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with an conditional branch and it falls through to
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/// an successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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/// 4. If this block ends with an conditional branch and an unconditional
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/// block, it returns the 'true' destination in TBB, the 'false' destination
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/// in FBB, and a list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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bool
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XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (IsBRU(LastInst->getOpcode())) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
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if (BranchCode == XCore::COND_INVALID)
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return true; // Can't handle indirect branch.
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// Conditional branch
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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Cond.push_back(LastInst->getOperand(0));
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return false;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isUnpredicatedTerminator(--I))
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return true;
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
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// If the block ends with conditional branch followed by unconditional,
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// handle it.
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if (BranchCode != XCore::COND_INVALID
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&& IsBRU(LastInst->getOpcode())) {
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TBB = SecondLastInst->getOperand(1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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Cond.push_back(SecondLastInst->getOperand(0));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The second
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// one is not executed, so remove it.
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if (IsBRU(SecondLastInst->getOpcode()) &&
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IsBRU(LastInst->getOpcode())) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned
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XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond)const{
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"Unexpected number of components!");
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if (FBB == 0) { // One way branch.
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if (Cond.empty()) {
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// Unconditional branch
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BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(TBB);
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} else {
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// Conditional branch.
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unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
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BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg())
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.addMBB(TBB);
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}
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return 1;
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}
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// Two-way Conditional branch.
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assert(Cond.size() == 2 && "Unexpected number of components!");
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unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
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BuildMI(&MBB, get(Opc)).addReg(Cond[1].getReg())
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.addMBB(TBB);
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BuildMI(&MBB, get(XCore::BRFU_lu6)).addMBB(FBB);
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return 2;
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}
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unsigned
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XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (!IsCondBranch(I->getOpcode()))
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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if (DestRC == SrcRC) {
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if (DestRC == XCore::GRRegsRegisterClass) {
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BuildMI(MBB, I, get(XCore::ADD_2rus), DestReg).addReg(SrcReg).addImm(0);
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return true;
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} else {
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return false;
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}
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}
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if (SrcRC == XCore::RRegsRegisterClass && SrcReg == XCore::SP &&
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DestRC == XCore::GRRegsRegisterClass) {
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BuildMI(MBB, I, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
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return true;
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}
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if (DestRC == XCore::RRegsRegisterClass && DestReg == XCore::SP &&
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SrcRC == XCore::GRRegsRegisterClass) {
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BuildMI(MBB, I, get(XCore::SETSP_1r)).addReg(SrcReg);
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return true;
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}
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return false;
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}
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void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const
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{
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BuildMI(MBB, I, get(XCore::STWFI)).addReg(SrcReg, false, false, isKill)
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.addFrameIndex(FrameIndex).addImm(0);
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}
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void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill, SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const
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{
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assert(0 && "unimplemented\n");
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}
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void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const
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{
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BuildMI(MBB, I, get(XCore::LDWFI), DestReg).addFrameIndex(FrameIndex)
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.addImm(0);
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}
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void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const
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{
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assert(0 && "unimplemented\n");
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}
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bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const
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{
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if (CSI.empty()) {
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return true;
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}
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
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XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
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bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
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for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
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it != CSI.end(); ++it) {
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(it->getReg());
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storeRegToStackSlot(MBB, MI, it->getReg(), true,
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it->getFrameIdx(), it->getRegClass());
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if (emitFrameMoves) {
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unsigned SaveLabelId = MMI->NextLabelID();
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BuildMI(MBB, MI, get(XCore::DBG_LABEL)).addImm(SaveLabelId);
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XFI->getSpillLabels().push_back(
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std::pair<unsigned, CalleeSavedInfo>(SaveLabelId, *it));
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}
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}
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return true;
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}
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bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const
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{
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bool AtStart = MI == MBB.begin();
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MachineBasicBlock::iterator BeforeI = MI;
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if (!AtStart)
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--BeforeI;
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for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
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it != CSI.end(); ++it) {
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loadRegFromStackSlot(MBB, MI, it->getReg(),
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it->getFrameIdx(),
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it->getRegClass());
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assert(MI != MBB.begin() &&
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"loadRegFromStackSlot didn't insert any code!");
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// Insert in reverse order. loadRegFromStackSlot can insert multiple
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// instructions.
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if (AtStart)
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MI = MBB.begin();
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else {
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MI = BeforeI;
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++MI;
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}
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}
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return true;
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}
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/// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
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/// fall-through into its successor block.
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bool XCoreInstrInfo::
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BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
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{
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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case XCore::RETSP_u6: // Return.
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case XCore::RETSP_lu6:
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case XCore::BAU_1r: // Indirect branch.
|
|
case XCore::BRFU_u6: // Uncond branch.
|
|
case XCore::BRFU_lu6:
|
|
case XCore::BRBU_u6:
|
|
case XCore::BRBU_lu6:
|
|
return true;
|
|
default: return false;
|
|
}
|
|
}
|
|
|
|
/// ReverseBranchCondition - Return the inverse opcode of the
|
|
/// specified Branch instruction.
|
|
bool XCoreInstrInfo::
|
|
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
|
|
{
|
|
assert((Cond.size() == 2) &&
|
|
"Invalid XCore branch condition!");
|
|
Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
|
|
return false;
|
|
}
|