NAKAMURA Takumi 7e6274dc66 llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176835 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-11 23:16:30 +00:00
..
AArch64	Test case hygiene.	2013-03-09 18:25:40 +00:00
ARM	Upgrading debug info test cases to be (more) compatible with the current debug info format.	2013-03-11 22:37:40 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Hexagon: Add patterns for zero extended loads from i1->i64.	2013-03-08 14:15:15 +00:00
Inputs	Upgrading debug info test cases to be (more) compatible with the current debug info format.	2013-03-11 22:37:40 +00:00
MBlaze	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
Mips	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
MSP430	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
NVPTX	[NVPTX] Disable vector registers	2013-02-12 14:18:49 +00:00
PowerPC	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
R600	llvm/test/CodeGen/R600/schedule-*.ll: Let them require +Asserts.	2013-03-11 23:16:30 +00:00
SI
SPARC	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
Thumb	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
Thumb2	SDAG: Handle scalarizing an extend of a <1 x iN> vector.	2013-03-07 05:47:54 +00:00
X86	Upgrading debug info test cases to be (more) compatible with the current debug info format.	2013-03-11 22:37:40 +00:00
XCore	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00