mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-19 17:33:29 +00:00
fc87928ebb
in the LLVM code generator sense (they are calls). Don't mark them as such, which fixes the regressions on the ppc tester last night git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22065 91177308-0d34-0410-b5e6-96231b3b80d8
504 lines
22 KiB
TableGen
504 lines
22 KiB
TableGen
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//===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the subset of the 32-bit PowerPC instruction set, as used
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// by the PowerPC instruction selector.
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//
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//===----------------------------------------------------------------------===//
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include "PowerPCInstrFormats.td"
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class isPPC64 { bit PPC64 = 1; }
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class isVMX { bit VMX = 1; }
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class isDOT {
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list<Register> Defs = [CR0];
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bit RC = 1;
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}
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let isTerminator = 1 in {
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let isReturn = 1 in
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def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
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def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
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}
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def u5imm : Operand<i8> {
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let PrintMethod = "printU5ImmOperand";
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}
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def u6imm : Operand<i8> {
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let PrintMethod = "printU6ImmOperand";
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}
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def s16imm : Operand<i16> {
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let PrintMethod = "printS16ImmOperand";
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}
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def u16imm : Operand<i16> {
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let PrintMethod = "printU16ImmOperand";
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}
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def target : Operand<i32> {
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let PrintMethod = "printBranchOperand";
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}
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def piclabel: Operand<i32> {
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let PrintMethod = "printPICLabel";
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}
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def symbolHi: Operand<i32> {
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let PrintMethod = "printSymbolHi";
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}
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def symbolLo: Operand<i32> {
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let PrintMethod = "printSymbolLo";
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}
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def crbit: Operand<i8> {
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let PrintMethod = "printcrbit";
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}
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// Pseudo-instructions:
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def PHI : Pseudo<(ops), "; PHI">;
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let isLoad = 1 in {
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def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
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def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
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}
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def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
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let isBranch = 1, isTerminator = 1 in {
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def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
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def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
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//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
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def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
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//def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
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// FIXME: 4*CR# needs to be added to the BI field!
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// This will only work for CR0 as it stands now
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def BLT : BForm_ext<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
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"blt $block">;
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def BLE : BForm_ext<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
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"ble $block">;
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def BEQ : BForm_ext<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
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"beq $block">;
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def BGE : BForm_ext<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
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"bge $block">;
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def BGT : BForm_ext<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
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"bgt $block">;
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def BNE : BForm_ext<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
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"bne $block">;
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}
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let isCall = 1,
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// All calls clobber the non-callee saved registers...
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Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
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LR,XER,CTR,
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CR0,CR1,CR5,CR6,CR7] in {
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// Convenient aliases for call instructions
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def CALLpcrel : IForm<18, 0, 1, (ops target:$func), "bl $func">;
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def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl">;
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}
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// D-Form instructions. Most instructions that perform an operation on a
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// register and an immediate are of this type.
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//
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let isLoad = 1 in {
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def LBZ : DForm_1<34, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lbz $rD, $disp($rA)">;
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def LHA : DForm_1<42, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lha $rD, $disp($rA)">;
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def LHZ : DForm_1<40, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lhz $rD, $disp($rA)">;
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def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lmw $rD, $disp($rA)">;
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def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lwz $rD, $disp($rA)">;
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def LWZU : DForm_1<35, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lwzu $rD, $disp($rA)">;
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}
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def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addi $rD, $rA, $imm">;
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def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addic $rD, $rA, $imm">;
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def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addic. $rD, $rA, $imm">;
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def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addis $rD, $rA, $imm">;
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def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
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"la $rD, $sym($rA)">;
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def LOADHiAddr : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
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"addis $rD, $rA, $sym">;
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def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"mulli $rD, $rA, $imm">;
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def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"subfic $rD, $rA, $imm">;
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def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
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"li $rD, $imm">;
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def LIS : DForm_2_r0<15, (ops GPRC:$rD, s16imm:$imm),
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"lis $rD, $imm">;
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let isStore = 1 in {
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def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stmw $rS, $disp($rA)">;
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def STB : DForm_3<38, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stb $rS, $disp($rA)">;
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def STH : DForm_3<44, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"sth $rS, $disp($rA)">;
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def STW : DForm_3<36, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stw $rS, $disp($rA)">;
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def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stwu $rS, $disp($rA)">;
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}
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def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2">, isDOT;
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def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2">, isDOT;
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def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2">;
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def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2">;
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def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2">;
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def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2">;
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def NOP : DForm_4_zero<24, (ops), "nop">;
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def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
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"cmpi $crD, $L, $rA, $imm">;
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def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
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"cmpwi $crD, $rA, $imm">;
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def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
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"cmpdi $crD, $rA, $imm">, isPPC64;
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def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
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"cmpli $dst, $size, $src1, $src2">;
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def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmplwi $dst, $src1, $src2">;
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def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2">, isPPC64;
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let isLoad = 1 in {
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def LFS : DForm_8<48, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lfs $rD, $disp($rA)">;
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def LFD : DForm_8<50, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lfd $rD, $disp($rA)">;
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}
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let isStore = 1 in {
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def STFS : DForm_9<52, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stfs $rS, $disp($rA)">;
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def STFD : DForm_9<54, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stfd $rS, $disp($rA)">;
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}
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// DS-Form instructions. Load/Store instructions available in PPC-64
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//
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let isLoad = 1 in {
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def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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"lwa $rT, $DS($rA)">, isPPC64;
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def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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"ld $rT, $DS($rA)">, isPPC64;
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}
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let isStore = 1 in {
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def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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"std $rT, $DS($rA)">, isPPC64;
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def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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"stdu $rT, $DS($rA)">, isPPC64;
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}
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// X-Form instructions. Most instructions that perform an operation on a
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// register and another register are of this type.
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//
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let isLoad = 1 in {
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def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lbzx $dst, $base, $index">;
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def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lhax $dst, $base, $index">;
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def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lhzx $dst, $base, $index">;
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def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lwax $dst, $base, $index">, isPPC64;
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def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lwzx $dst, $base, $index">;
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def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"ldx $dst, $base, $index">, isPPC64;
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}
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def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and $rA, $rS, $rB">;
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def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and. $rA, $rS, $rB">, isDOT;
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def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"andc $rA, $rS, $rB">;
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def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"eqv $rA, $rS, $rB">;
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def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nand $rA, $rS, $rB">;
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def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nor $rA, $rS, $rB">;
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def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or $rA, $rS, $rB">;
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def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or. $rA, $rS, $rB">, isDOT;
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def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"orc $rA, $rS, $rB">;
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def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sld $rA, $rS, $rB">, isPPC64;
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def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"slw $rA, $rS, $rB">;
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def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srd $rA, $rS, $rB">, isPPC64;
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def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srw $rA, $rS, $rB">;
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def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srad $rA, $rS, $rB">, isPPC64;
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def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sraw $rA, $rS, $rB">;
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def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"xor $rA, $rS, $rB">;
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let isStore = 1 in {
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def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stbx $rS, $rA, $rB">;
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def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"sthx $rS, $rA, $rB">;
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def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stwx $rS, $rA, $rB">;
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def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stwux $rS, $rA, $rB">;
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def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdx $rS, $rA, $rB">, isPPC64;
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def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdux $rS, $rA, $rB">, isPPC64;
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}
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def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
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"srawi $rA, $rS, $SH">;
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def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
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"cntlzw $rA, $rS">;
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def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
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"extsb $rA, $rS">;
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def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
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"extsh $rA, $rS">;
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def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
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"extsw $rA, $rS">, isPPC64;
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def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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"cmp $crD, $long, $rA, $rB">;
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def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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"cmpl $crD, $long, $rA, $rB">;
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def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpw $crD, $rA, $rB">;
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def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpd $crD, $rA, $rB">, isPPC64;
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def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmplw $crD, $rA, $rB">;
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def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpld $crD, $rA, $rB">, isPPC64;
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def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
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"fcmpo $crD, $fA, $fB">;
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def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
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"fcmpu $crD, $fA, $fB">;
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let isLoad = 1 in {
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def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
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"lfsx $dst, $base, $index">;
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def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
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"lfdx $dst, $base, $index">;
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}
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def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
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"fcfid $frD, $frB">, isPPC64;
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def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
|
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"fctidz $frD, $frB">, isPPC64;
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def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
|
|
"fctiwz $frD, $frB">;
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def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
|
|
"fabs $frD, $frB">;
|
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def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
|
|
"fmr $frD, $frB">;
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def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
|
|
"fnabs $frD, $frB">;
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def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
|
|
"fneg $frD, $frB">;
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def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
|
|
"frsp $frD, $frB">;
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let isStore = 1 in {
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|
def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
|
|
"stfsx $frS, $rA, $rB">;
|
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def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
|
|
"stfdx $frS, $rA, $rB">;
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}
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// XL-Form instructions. condition register logical ops.
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//
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def CRAND : XLForm_1<19, 257, (ops CRRC:$D, crbit:$Db,
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CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
|
"crand $Db, $Ab, $Bb">;
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def CRANDC : XLForm_1<19, 129, (ops CRRC:$D, crbit:$Db,
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CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
|
"crandc $Db, $Ab, $Bb">;
|
|
def CREQV : XLForm_1<19, 289, (ops CRRC:$D, crbit:$Db,
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|
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
|
"creqv $Db, $Ab, $Bb">;
|
|
def CRNAND : XLForm_1<19, 225, (ops CRRC:$D, crbit:$Db,
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CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
|
"crnand $Db, $Ab, $Bb">;
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def CRNOR : XLForm_1<19, 33, (ops CRRC:$D, crbit:$Db,
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|
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
|
"crnor $Db, $Ab, $Bb">;
|
|
def CROR : XLForm_1<19, 449, (ops CRRC:$D, crbit:$Db,
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|
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
|
"cror $Db, $Ab, $Bb">;
|
|
def CRORC : XLForm_1<19, 417, (ops CRRC:$D, crbit:$Db,
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|
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
|
"crorc $Db, $Ab, $Bb">;
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|
def CRXOR : XLForm_1<19, 193, (ops CRRC:$D, crbit:$Db,
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|
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
|
"crxor $Db, $Ab, $Bb">;
|
|
def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
|
|
"mcrf $BF, $BFA">;
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|
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// XFX-Form instructions. Instructions that deal with SPRs
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|
//
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|
// Note that although LR should be listed as `8' and CTR as `9' in the SPR
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|
// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
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// which means the SPR value needs to be multiplied by a factor of 32.
|
|
def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
|
|
def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
|
|
def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
|
|
def MTCRF : XFXForm_5<31, 0, 144, (ops CRRC:$FXM, GPRC:$rS),
|
|
"mtcrf $FXM, $rS">;
|
|
def MFCRF : XFXForm_5<31, 1, 19, (ops GPRC:$rT, CRRC:$FXM),
|
|
"mfcr $rT, $FXM">;
|
|
def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
|
|
def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
|
|
|
|
// XS-Form instructions. Just 'sradi'
|
|
//
|
|
def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
|
|
"sradi $rA, $rS, $SH">, isPPC64;
|
|
|
|
// XO-Form instructions. Arithmetic instructions that can set overflow bit
|
|
//
|
|
def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"add $rT, $rA, $rB">;
|
|
def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"addc $rT, $rA, $rB">;
|
|
def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"adde $rT, $rA, $rB">;
|
|
def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"divd $rT, $rA, $rB">, isPPC64;
|
|
def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"divdu $rT, $rA, $rB">, isPPC64;
|
|
def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"divw $rT, $rA, $rB">;
|
|
def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"divwu $rT, $rA, $rB">;
|
|
def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"mulhw $rT, $rA, $rB">;
|
|
def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"mulhwu $rT, $rA, $rB">;
|
|
def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"mulld $rT, $rA, $rB">, isPPC64;
|
|
def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"mullw $rT, $rA, $rB">;
|
|
def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"subf $rT, $rA, $rB">;
|
|
def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"subfc $rT, $rA, $rB">;
|
|
def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"subfe $rT, $rA, $rB">;
|
|
def SUB : XOForm_1r<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
|
|
"sub $rT, $rA, $rB">;
|
|
def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
|
|
"addme $rT, $rA">;
|
|
def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
|
|
"addze $rT, $rA">;
|
|
def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
|
|
"neg $rT, $rA">;
|
|
def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
|
|
"subfze $rT, $rA">;
|
|
|
|
// A-Form instructions. Most of the instructions executed in the FPU are of
|
|
// this type.
|
|
//
|
|
def FMADD : AForm_1<63, 29,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fmadd $FRT, $FRA, $FRC, $FRB">;
|
|
def FMADDS : AForm_1<59, 29,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fmadds $FRT, $FRA, $FRC, $FRB">;
|
|
def FMSUB : AForm_1<63, 28,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fmsub $FRT, $FRA, $FRC, $FRB">;
|
|
def FMSUBS : AForm_1<59, 28,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fmsubs $FRT, $FRA, $FRC, $FRB">;
|
|
def FNMADD : AForm_1<63, 31,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fnmadd $FRT, $FRA, $FRC, $FRB">;
|
|
def FNMADDS : AForm_1<59, 31,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fnmadds $FRT, $FRA, $FRC, $FRB">;
|
|
def FNMSUB : AForm_1<63, 30,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fnmsub $FRT, $FRA, $FRC, $FRB">;
|
|
def FNMSUBS : AForm_1<59, 30,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fnmsubs $FRT, $FRA, $FRC, $FRB">;
|
|
def FSEL : AForm_1<63, 23,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
|
|
"fsel $FRT, $FRA, $FRC, $FRB">;
|
|
def FADD : AForm_2<63, 21,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
|
"fadd $FRT, $FRA, $FRB">;
|
|
def FADDS : AForm_2<59, 21,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
|
"fadds $FRT, $FRA, $FRB">;
|
|
def FDIV : AForm_2<63, 18,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
|
"fdiv $FRT, $FRA, $FRB">;
|
|
def FDIVS : AForm_2<59, 18,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
|
"fdivs $FRT, $FRA, $FRB">;
|
|
def FMUL : AForm_3<63, 25,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
|
"fmul $FRT, $FRA, $FRB">;
|
|
def FMULS : AForm_3<59, 25,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
|
"fmuls $FRT, $FRA, $FRB">;
|
|
def FSUB : AForm_2<63, 20,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
|
"fsub $FRT, $FRA, $FRB">;
|
|
def FSUBS : AForm_2<59, 20,
|
|
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
|
|
"fsubs $FRT, $FRA, $FRB">;
|
|
|
|
// M-Form instructions. rotate and mask instructions.
|
|
//
|
|
let isTwoAddress = 1 in {
|
|
def RLWIMI : MForm_2<20,
|
|
(ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
|
|
u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
|
|
}
|
|
def RLWINM : MForm_2<21,
|
|
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
|
"rlwinm $rA, $rS, $SH, $MB, $ME">;
|
|
def RLWINMo : MForm_2<21,
|
|
(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
|
"rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
|
|
def RLWNM : MForm_2<23,
|
|
(ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
|
|
"rlwnm $rA, $rS, $rB, $MB, $ME">;
|
|
|
|
// MD-Form instructions. 64 bit rotate instructions.
|
|
//
|
|
def RLDICL : MDForm_1<30, 0,
|
|
(ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
|
|
"rldicl $rA, $rS, $SH, $MB">, isPPC64;
|
|
def RLDICR : MDForm_1<30, 1,
|
|
(ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
|
|
"rldicr $rA, $rS, $SH, $ME">, isPPC64;
|
|
|
|
def PowerPCInstrInfo : InstrInfo {
|
|
let PHIInst = PHI;
|
|
|
|
let TSFlagsFields = [ "VMX", "PPC64" ];
|
|
let TSFlagsShifts = [ 0, 1 ];
|
|
|
|
let isLittleEndianEncoding = 1;
|
|
}
|
|
|