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TargetMachine.cpp, since it is entirely machine-independent. Also, add options to disable optional back-end passes (preselection and instr. scheduling). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3740 91177308-0d34-0410-b5e6-96231b3b80d8
168 lines
6.4 KiB
C++
168 lines
6.4 KiB
C++
//===-- PrologEpilogCodeInserter.cpp - Insert Prolog & Epilog code for fn -===//
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//
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// Insert SAVE/RESTORE instructions for the function
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//
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// Insert prolog code at the unique function entry point.
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// Insert epilog code at each function exit point.
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// InsertPrologEpilog invokes these only if the function is not compiled
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// with the leaf function optimization.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInternals.h"
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#include "SparcRegClassInfo.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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namespace {
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class InsertPrologEpilogCode : public FunctionPass {
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TargetMachine &Target;
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public:
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InsertPrologEpilogCode(TargetMachine &T) : Target(T) {}
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const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; }
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bool runOnFunction(Function &F) {
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MachineCodeForMethod &mcodeInfo = MachineCodeForMethod::get(&F);
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if (!mcodeInfo.isCompiledAsLeafMethod()) {
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InsertPrologCode(F);
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InsertEpilogCode(F);
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}
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return false;
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}
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void InsertPrologCode(Function &F);
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void InsertEpilogCode(Function &F);
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};
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} // End anonymous namespace
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//------------------------------------------------------------------------
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// External Function: GetInstructionsForProlog
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// External Function: GetInstructionsForEpilog
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//
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// Purpose:
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// Create prolog and epilog code for procedure entry and exit
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//------------------------------------------------------------------------
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void InsertPrologEpilogCode::InsertPrologCode(Function &F)
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{
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std::vector<MachineInstr*> mvec;
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MachineInstr* M;
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const MachineFrameInfo& frameInfo = Target.getFrameInfo();
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// The second operand is the stack size. If it does not fit in the
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// immediate field, we have to use a free register to hold the size.
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// We will assume that local register `l0' is unused since the SAVE
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// instruction must be the first instruction in each procedure.
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//
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MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(&F);
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unsigned int staticStackSize = mcInfo.getStaticStackSize();
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if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize())
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staticStackSize = (unsigned) frameInfo.getMinStackFrameSize();
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if (unsigned padsz = (staticStackSize %
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(unsigned) frameInfo.getStackFrameSizeAlignment()))
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staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz;
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if (Target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize))
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{
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M = new MachineInstr(SAVE);
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M->SetMachineOperandReg(0, Target.getRegInfo().getStackPointer());
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M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
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- (int) staticStackSize);
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M->SetMachineOperandReg(2, Target.getRegInfo().getStackPointer());
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mvec.push_back(M);
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}
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else
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{
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// We have to put the stack size value into a register before SAVE.
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// Use register %l0 to since it must be unused at function entry.
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// Do this by creating a code sequence equivalent to:
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// SETSW -(stackSize), %l0
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int32_t C = - (int) staticStackSize;
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int uregNum = Target.getRegInfo().getUnifiedRegNum(
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Target.getRegInfo().getRegClassIDOfType(Type::IntTy),
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SparcIntRegClass::l0);
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M = new MachineInstr(SETHI);
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M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed, C);
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M->SetMachineOperandReg(1, uregNum);
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M->setOperandHi32(0);
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mvec.push_back(M);
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M = new MachineInstr(OR);
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M->SetMachineOperandReg(0, uregNum);
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M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed, C);
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M->SetMachineOperandReg(2, uregNum);
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M->setOperandLo32(1);
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mvec.push_back(M);
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M = new MachineInstr(SRA);
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M->SetMachineOperandReg(0, uregNum);
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M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed, 0);
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M->SetMachineOperandReg(2, uregNum);
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mvec.push_back(M);
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// Now generate the SAVE using the value in register %l0
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M = new MachineInstr(SAVE);
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M->SetMachineOperandReg(0, Target.getRegInfo().getStackPointer());
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M->SetMachineOperandReg(1, uregNum);
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M->SetMachineOperandReg(2, Target.getRegInfo().getStackPointer());
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mvec.push_back(M);
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}
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MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(&F.getEntryNode());
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bbMvec.insert(bbMvec.begin(), mvec.begin(), mvec.end());
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}
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void InsertPrologEpilogCode::InsertEpilogCode(Function &F)
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{
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for (Function::iterator I = F.begin(), E = F.end(); I != E; ++I) {
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Instruction *TermInst = (Instruction*)I->getTerminator();
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if (TermInst->getOpcode() == Instruction::Ret)
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{
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MachineInstr *Restore = new MachineInstr(RESTORE);
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Restore->SetMachineOperandReg(0, Target.getRegInfo().getZeroRegNum());
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Restore->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
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(int64_t)0);
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Restore->SetMachineOperandReg(2, Target.getRegInfo().getZeroRegNum());
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MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(I);
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MachineCodeForInstruction &termMvec =
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MachineCodeForInstruction::get(TermInst);
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// Remove the NOPs in the delay slots of the return instruction
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const MachineInstrInfo &mii = Target.getInstrInfo();
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unsigned numNOPs = 0;
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while (termMvec.back()->getOpCode() == NOP)
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{
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assert( termMvec.back() == bbMvec.back());
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delete bbMvec.pop_back();
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termMvec.pop_back();
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++numNOPs;
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}
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assert(termMvec.back() == bbMvec.back());
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// Check that we found the right number of NOPs and have the right
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// number of instructions to replace them.
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unsigned ndelays = mii.getNumDelaySlots(termMvec.back()->getOpCode());
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assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
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assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
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// Append the epilog code to the end of the basic block.
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bbMvec.push_back(Restore);
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}
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}
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}
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Pass* UltraSparc::getPrologEpilogInsertionPass() {
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return new InsertPrologEpilogCode(*this);
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}
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