mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ac6d9bec67
Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
749 lines
26 KiB
C++
749 lines
26 KiB
C++
//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEISelLowering.h"
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#include "MipsRegisterInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
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cl::desc("MIPS: Enable tail calls."), cl::init(false));
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MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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: MipsTargetLowering(TM) {
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// Set up the register classes
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clearRegisterClasses();
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addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
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if (HasMips64)
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addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
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if (Subtarget->hasDSP()) {
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MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
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for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
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addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
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// Expand all builtin opcodes.
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for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
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setOperationAction(Opc, VecTys[i], Expand);
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setOperationAction(ISD::ADD, VecTys[i], Legal);
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setOperationAction(ISD::SUB, VecTys[i], Legal);
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setOperationAction(ISD::LOAD, VecTys[i], Legal);
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setOperationAction(ISD::STORE, VecTys[i], Legal);
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setOperationAction(ISD::BITCAST, VecTys[i], Legal);
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}
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setTargetDAGCombine(ISD::SHL);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::SETCC);
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setTargetDAGCombine(ISD::VSELECT);
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}
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if (Subtarget->hasDSPR2())
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setOperationAction(ISD::MUL, MVT::v2i16, Legal);
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if (!TM.Options.UseSoftFloat) {
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addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
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// When dealing with single precision only, use libcalls
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if (!Subtarget->isSingleFloat()) {
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if (HasMips64)
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addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
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else
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addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
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}
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}
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
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setOperationAction(ISD::MULHS, MVT::i32, Custom);
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setOperationAction(ISD::MULHU, MVT::i32, Custom);
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if (HasMips64) {
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setOperationAction(ISD::MULHS, MVT::i64, Custom);
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setOperationAction(ISD::MULHU, MVT::i64, Custom);
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setOperationAction(ISD::MUL, MVT::i64, Custom);
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}
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
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setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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setOperationAction(ISD::LOAD, MVT::i32, Custom);
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setOperationAction(ISD::STORE, MVT::i32, Custom);
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setTargetDAGCombine(ISD::ADDE);
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setTargetDAGCombine(ISD::SUBE);
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computeRegisterProperties();
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}
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const MipsTargetLowering *
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llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
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return new MipsSETargetLowering(TM);
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}
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bool
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MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
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MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
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switch (SVT) {
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case MVT::i64:
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case MVT::i32:
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if (Fast)
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*Fast = true;
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return true;
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default:
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return false;
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}
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}
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SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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switch(Op.getOpcode()) {
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case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
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case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
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case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
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case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
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case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
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case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
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case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
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DAG);
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case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
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}
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return MipsTargetLowering::LowerOperation(Op, DAG);
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}
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// selectMADD -
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// Transforms a subgraph in CurDAG if the following pattern is found:
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// (addc multLo, Lo0), (adde multHi, Hi0),
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// where,
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// multHi/Lo: product of multiplication
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// Lo0: initial value of Lo register
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// Hi0: initial value of Hi register
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// Return true if pattern matching was successful.
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static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
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// ADDENode's second operand must be a flag output of an ADDC node in order
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// for the matching to be successful.
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SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
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if (ADDCNode->getOpcode() != ISD::ADDC)
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return false;
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SDValue MultHi = ADDENode->getOperand(0);
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SDValue MultLo = ADDCNode->getOperand(0);
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SDNode *MultNode = MultHi.getNode();
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unsigned MultOpc = MultHi.getOpcode();
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// MultHi and MultLo must be generated by the same node,
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if (MultLo.getNode() != MultNode)
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return false;
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// and it must be a multiplication.
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if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
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return false;
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// MultLo amd MultHi must be the first and second output of MultNode
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// respectively.
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if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
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return false;
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// Transform this to a MADD only if ADDENode and ADDCNode are the only users
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// of the values of MultNode, in which case MultNode will be removed in later
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// phases.
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// If there exist users other than ADDENode or ADDCNode, this function returns
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// here, which will result in MultNode being mapped to a single MULT
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// instruction node rather than a pair of MULT and MADD instructions being
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// produced.
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if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
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return false;
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SDLoc DL(ADDENode);
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// Initialize accumulator.
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SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
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ADDCNode->getOperand(1),
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ADDENode->getOperand(1));
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// create MipsMAdd(u) node
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MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
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SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
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MultNode->getOperand(0),// Factor 0
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MultNode->getOperand(1),// Factor 1
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ACCIn);
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// replace uses of adde and addc here
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if (!SDValue(ADDCNode, 0).use_empty()) {
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SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
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SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
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LoIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
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}
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if (!SDValue(ADDENode, 0).use_empty()) {
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SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
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SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
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HiIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
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}
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return true;
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}
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// selectMSUB -
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// Transforms a subgraph in CurDAG if the following pattern is found:
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// (addc Lo0, multLo), (sube Hi0, multHi),
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// where,
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// multHi/Lo: product of multiplication
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// Lo0: initial value of Lo register
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// Hi0: initial value of Hi register
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// Return true if pattern matching was successful.
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static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
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// SUBENode's second operand must be a flag output of an SUBC node in order
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// for the matching to be successful.
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SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
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if (SUBCNode->getOpcode() != ISD::SUBC)
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return false;
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SDValue MultHi = SUBENode->getOperand(1);
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SDValue MultLo = SUBCNode->getOperand(1);
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SDNode *MultNode = MultHi.getNode();
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unsigned MultOpc = MultHi.getOpcode();
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// MultHi and MultLo must be generated by the same node,
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if (MultLo.getNode() != MultNode)
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return false;
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// and it must be a multiplication.
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if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
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return false;
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// MultLo amd MultHi must be the first and second output of MultNode
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// respectively.
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if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
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return false;
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// Transform this to a MSUB only if SUBENode and SUBCNode are the only users
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// of the values of MultNode, in which case MultNode will be removed in later
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// phases.
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// If there exist users other than SUBENode or SUBCNode, this function returns
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// here, which will result in MultNode being mapped to a single MULT
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// instruction node rather than a pair of MULT and MSUB instructions being
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// produced.
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if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
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return false;
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SDLoc DL(SUBENode);
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// Initialize accumulator.
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SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
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SUBCNode->getOperand(0),
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SUBENode->getOperand(0));
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// create MipsSub(u) node
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MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
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SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
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MultNode->getOperand(0),// Factor 0
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MultNode->getOperand(1),// Factor 1
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ACCIn);
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// replace uses of sube and subc here
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if (!SDValue(SUBCNode, 0).use_empty()) {
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SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
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SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
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LoIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
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}
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if (!SDValue(SUBENode, 0).use_empty()) {
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SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
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SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
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HiIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
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}
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return true;
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}
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static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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if (DCI.isBeforeLegalize())
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return SDValue();
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if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
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selectMADD(N, &DAG))
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return SDValue(N, 0);
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return SDValue();
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}
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static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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if (DCI.isBeforeLegalize())
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return SDValue();
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if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
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selectMSUB(N, &DAG))
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return SDValue(N, 0);
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return SDValue();
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}
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static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
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SelectionDAG &DAG,
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const MipsSubtarget *Subtarget) {
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// See if this is a vector splat immediate node.
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APInt SplatValue, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
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BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
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if (!BV ||
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!BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
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EltSize, !Subtarget->isLittle()) ||
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(SplatBitSize != EltSize) ||
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(SplatValue.getZExtValue() >= EltSize))
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return SDValue();
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return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
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DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
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}
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static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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EVT Ty = N->getValueType(0);
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if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
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return SDValue();
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return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
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}
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static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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EVT Ty = N->getValueType(0);
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if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
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return SDValue();
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return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
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}
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static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const MipsSubtarget *Subtarget) {
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EVT Ty = N->getValueType(0);
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if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
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return SDValue();
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return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
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}
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static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
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bool IsV216 = (Ty == MVT::v2i16);
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switch (CC) {
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case ISD::SETEQ:
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case ISD::SETNE: return true;
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case ISD::SETLT:
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case ISD::SETLE:
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case ISD::SETGT:
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case ISD::SETGE: return IsV216;
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case ISD::SETULT:
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case ISD::SETULE:
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case ISD::SETUGT:
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case ISD::SETUGE: return !IsV216;
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default: return false;
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}
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}
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static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
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EVT Ty = N->getValueType(0);
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if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
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return SDValue();
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if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
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return SDValue();
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return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
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N->getOperand(1), N->getOperand(2));
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}
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static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
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EVT Ty = N->getValueType(0);
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if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
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return SDValue();
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SDValue SetCC = N->getOperand(0);
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if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
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return SDValue();
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return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
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SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
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N->getOperand(2), SetCC.getOperand(2));
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}
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SDValue
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MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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SDValue Val;
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switch (N->getOpcode()) {
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case ISD::ADDE:
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return performADDECombine(N, DAG, DCI, Subtarget);
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case ISD::SUBE:
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return performSUBECombine(N, DAG, DCI, Subtarget);
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case ISD::SHL:
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return performSHLCombine(N, DAG, DCI, Subtarget);
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case ISD::SRA:
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return performSRACombine(N, DAG, DCI, Subtarget);
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case ISD::SRL:
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return performSRLCombine(N, DAG, DCI, Subtarget);
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case ISD::VSELECT:
|
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return performVSELECTCombine(N, DAG);
|
|
case ISD::SETCC: {
|
|
Val = performSETCCCombine(N, DAG);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (Val.getNode())
|
|
return Val;
|
|
|
|
return MipsTargetLowering::PerformDAGCombine(N, DCI);
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *BB) const {
|
|
switch (MI->getOpcode()) {
|
|
default:
|
|
return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
|
|
case Mips::BPOSGE32_PSEUDO:
|
|
return emitBPOSGE32(MI, BB);
|
|
}
|
|
}
|
|
|
|
bool MipsSETargetLowering::
|
|
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
|
|
unsigned NextStackOffset,
|
|
const MipsFunctionInfo& FI) const {
|
|
if (!EnableMipsTailCalls)
|
|
return false;
|
|
|
|
// Return false if either the callee or caller has a byval argument.
|
|
if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
|
|
return false;
|
|
|
|
// Return true if the callee's argument area is no larger than the
|
|
// caller's.
|
|
return NextStackOffset <= FI.getIncomingArgSize();
|
|
}
|
|
|
|
void MipsSETargetLowering::
|
|
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
|
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
|
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
|
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
|
|
// T9 should contain the address of the callee function if
|
|
// -reloction-model=pic or it is an indirect call.
|
|
if (IsPICCall || !GlobalOrExternal) {
|
|
unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
|
|
RegsToPass.push_front(std::make_pair(T9Reg, Callee));
|
|
} else
|
|
Ops.push_back(Callee);
|
|
|
|
MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
|
|
InternalLinkage, CLI, Callee, Chain);
|
|
}
|
|
|
|
SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
|
|
bool HasLo, bool HasHi,
|
|
SelectionDAG &DAG) const {
|
|
EVT Ty = Op.getOperand(0).getValueType();
|
|
SDLoc DL(Op);
|
|
SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
|
|
Op.getOperand(0), Op.getOperand(1));
|
|
SDValue Lo, Hi;
|
|
|
|
if (HasLo)
|
|
Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
|
|
DAG.getConstant(Mips::sub_lo, MVT::i32));
|
|
if (HasHi)
|
|
Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
|
|
DAG.getConstant(Mips::sub_hi, MVT::i32));
|
|
|
|
if (!HasLo || !HasHi)
|
|
return HasLo ? Lo : Hi;
|
|
|
|
SDValue Vals[] = { Lo, Hi };
|
|
return DAG.getMergeValues(Vals, 2, DL);
|
|
}
|
|
|
|
|
|
static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
|
|
SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
|
|
DAG.getConstant(0, MVT::i32));
|
|
SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
|
|
DAG.getConstant(1, MVT::i32));
|
|
return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
|
|
}
|
|
|
|
static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
|
|
SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
|
|
DAG.getConstant(Mips::sub_lo, MVT::i32));
|
|
SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
|
|
DAG.getConstant(Mips::sub_hi, MVT::i32));
|
|
return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
|
|
}
|
|
|
|
// This function expands mips intrinsic nodes which have 64-bit input operands
|
|
// or output values.
|
|
//
|
|
// out64 = intrinsic-node in64
|
|
// =>
|
|
// lo = copy (extract-element (in64, 0))
|
|
// hi = copy (extract-element (in64, 1))
|
|
// mips-specific-node
|
|
// v0 = copy lo
|
|
// v1 = copy hi
|
|
// out64 = merge-values (v0, v1)
|
|
//
|
|
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
|
SDLoc DL(Op);
|
|
bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
|
|
SmallVector<SDValue, 3> Ops;
|
|
unsigned OpNo = 0;
|
|
|
|
// See if Op has a chain input.
|
|
if (HasChainIn)
|
|
Ops.push_back(Op->getOperand(OpNo++));
|
|
|
|
// The next operand is the intrinsic opcode.
|
|
assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
|
|
|
|
// See if the next operand has type i64.
|
|
SDValue Opnd = Op->getOperand(++OpNo), In64;
|
|
|
|
if (Opnd.getValueType() == MVT::i64)
|
|
In64 = initAccumulator(Opnd, DL, DAG);
|
|
else
|
|
Ops.push_back(Opnd);
|
|
|
|
// Push the remaining operands.
|
|
for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
|
|
Ops.push_back(Op->getOperand(OpNo));
|
|
|
|
// Add In64 to the end of the list.
|
|
if (In64.getNode())
|
|
Ops.push_back(In64);
|
|
|
|
// Scan output.
|
|
SmallVector<EVT, 2> ResTys;
|
|
|
|
for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
|
|
I != E; ++I)
|
|
ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
|
|
|
|
// Create node.
|
|
SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
|
|
SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
|
|
|
|
if (!HasChainIn)
|
|
return Out;
|
|
|
|
assert(Val->getValueType(1) == MVT::Other);
|
|
SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
|
|
return DAG.getMergeValues(Vals, 2, DL);
|
|
}
|
|
|
|
SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
|
|
default:
|
|
return SDValue();
|
|
case Intrinsic::mips_shilo:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
|
|
case Intrinsic::mips_dpau_h_qbl:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
|
|
case Intrinsic::mips_dpau_h_qbr:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
|
|
case Intrinsic::mips_dpsu_h_qbl:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
|
|
case Intrinsic::mips_dpsu_h_qbr:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
|
|
case Intrinsic::mips_dpa_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
|
|
case Intrinsic::mips_dps_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
|
|
case Intrinsic::mips_dpax_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
|
|
case Intrinsic::mips_dpsx_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
|
|
case Intrinsic::mips_mulsa_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
|
|
case Intrinsic::mips_mult:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::Mult);
|
|
case Intrinsic::mips_multu:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::Multu);
|
|
case Intrinsic::mips_madd:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
|
|
case Intrinsic::mips_maddu:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
|
|
case Intrinsic::mips_msub:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MSub);
|
|
case Intrinsic::mips_msubu:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
|
|
}
|
|
}
|
|
|
|
SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
|
|
default:
|
|
return SDValue();
|
|
case Intrinsic::mips_extp:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
|
|
case Intrinsic::mips_extpdp:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
|
|
case Intrinsic::mips_extr_w:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
|
|
case Intrinsic::mips_extr_r_w:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
|
|
case Intrinsic::mips_extr_rs_w:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
|
|
case Intrinsic::mips_extr_s_h:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
|
|
case Intrinsic::mips_mthlip:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
|
|
case Intrinsic::mips_mulsaq_s_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
|
|
case Intrinsic::mips_maq_s_w_phl:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
|
|
case Intrinsic::mips_maq_s_w_phr:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
|
|
case Intrinsic::mips_maq_sa_w_phl:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
|
|
case Intrinsic::mips_maq_sa_w_phr:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
|
|
case Intrinsic::mips_dpaq_s_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
|
|
case Intrinsic::mips_dpsq_s_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
|
|
case Intrinsic::mips_dpaq_sa_l_w:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
|
|
case Intrinsic::mips_dpsq_sa_l_w:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
|
|
case Intrinsic::mips_dpaqx_s_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
|
|
case Intrinsic::mips_dpaqx_sa_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
|
|
case Intrinsic::mips_dpsqx_s_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
|
|
case Intrinsic::mips_dpsqx_sa_w_ph:
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
|
|
}
|
|
}
|
|
|
|
MachineBasicBlock * MipsSETargetLowering::
|
|
emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
|
|
// $bb:
|
|
// bposge32_pseudo $vr0
|
|
// =>
|
|
// $bb:
|
|
// bposge32 $tbb
|
|
// $fbb:
|
|
// li $vr2, 0
|
|
// b $sink
|
|
// $tbb:
|
|
// li $vr1, 1
|
|
// $sink:
|
|
// $vr0 = phi($vr2, $fbb, $vr1, $tbb)
|
|
|
|
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
|
|
F->insert(It, FBB);
|
|
F->insert(It, TBB);
|
|
F->insert(It, Sink);
|
|
|
|
// Transfer the remainder of BB and its successor edges to Sink.
|
|
Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
|
|
BB->end());
|
|
Sink->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
// Add successors.
|
|
BB->addSuccessor(FBB);
|
|
BB->addSuccessor(TBB);
|
|
FBB->addSuccessor(Sink);
|
|
TBB->addSuccessor(Sink);
|
|
|
|
// Insert the real bposge32 instruction to $BB.
|
|
BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
|
|
|
|
// Fill $FBB.
|
|
unsigned VR2 = RegInfo.createVirtualRegister(RC);
|
|
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
|
|
.addReg(Mips::ZERO).addImm(0);
|
|
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
|
|
|
|
// Fill $TBB.
|
|
unsigned VR1 = RegInfo.createVirtualRegister(RC);
|
|
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
|
|
.addReg(Mips::ZERO).addImm(1);
|
|
|
|
// Insert phi function to $Sink.
|
|
BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
|
|
MI->getOperand(0).getReg())
|
|
.addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
|
|
|
|
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
|
return Sink;
|
|
}
|