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https://github.com/c64scene-ar/llvm-6502.git
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2012cc013c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24020 91177308-0d34-0410-b5e6-96231b3b80d8
289 lines
10 KiB
C++
289 lines
10 KiB
C++
//===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Andrew Lenharth and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for Alpha,
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// converting from a legalized dag to a Alpha dag.
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaTargetMachine.h"
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#include "AlphaISelLowering.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Constants.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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using namespace llvm;
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namespace {
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//===--------------------------------------------------------------------===//
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/// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
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/// instructions for SelectionDAG operations.
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///
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class AlphaDAGToDAGISel : public SelectionDAGISel {
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AlphaTargetLowering AlphaLowering;
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public:
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AlphaDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDOperand getI64Imm(int64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand Select(SDOperand Op);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "Alpha DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "AlphaGenDAGISel.inc"
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private:
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SDOperand getGlobalBaseReg();
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SDOperand SelectCALL(SDOperand Op);
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};
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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///
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SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
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return CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64);
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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DAG.setRoot(Select(DAG.getRoot()));
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
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N->getOpcode() < AlphaISD::FIRST_NUMBER)
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return Op; // Already selected.
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// If this has already been converted, use it.
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std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
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if (CGMI != CodeGenMap.end()) return CGMI->second;
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switch (N->getOpcode()) {
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default: break;
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case ISD::TAILCALL:
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case ISD::CALL: return SelectCALL(Op);
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case ISD::DYNAMIC_STACKALLOC:
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assert(0 && "You want these too?");
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case ISD::BRCOND: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand CC = Select(N->getOperand(1));
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CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, Chain);
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return SDOperand(N, 0);
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}
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case ISD::LOAD:
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case ISD::EXTLOAD:
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case ISD::ZEXTLOAD:
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case ISD::SEXTLOAD: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Address = Select(N->getOperand(1));
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unsigned opcode = N->getOpcode();
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unsigned Opc = Alpha::WTF;
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if (opcode == ISD::LOAD)
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switch (N->getValueType(0)) {
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default: N->dump(); assert(0 && "Bad load!");
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case MVT::i64: Opc = Alpha::LDQ; break;
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case MVT::f64: Opc = Alpha::LDT; break;
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case MVT::f32: Opc = Alpha::LDS; break;
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}
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else
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switch (cast<VTSDNode>(N->getOperand(3))->getVT()) {
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default: N->dump(); assert(0 && "Bad sign extend!");
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case MVT::i32: Opc = Alpha::LDL;
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assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
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case MVT::i16: Opc = Alpha::LDWU;
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
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case MVT::i8: Opc = Alpha::LDBU;
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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}
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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getI64Imm(0), Address, Chain);
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return SDOperand(N, Op.ResNo);
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}
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case ISD::BR: {
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CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1),
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Select(N->getOperand(0)));
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return SDOperand(N, 0);
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}
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case ISD::UNDEF:
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if (N->getValueType(0) == MVT::i64)
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CurDAG->SelectNodeTo(N, Alpha::IDEF, MVT::i64);
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// else if (N->getValueType(0) == MVT::f32)
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// CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F4, MVT::f32);
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// else
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// CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F8, MVT::f64);
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return SDOperand(N, 0);
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case ISD::FrameIndex: {
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// int FI = cast<FrameIndexSDNode>(N)->getIndex();
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// CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
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// CurDAG->getTargetFrameIndex(FI, MVT::i32),
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// getI32Imm(0));
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// return SDOperand(N, 0);
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assert(0 && "Frame?, you are suppose to look through the window, not at the frame!");
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}
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case ISD::ConstantPool: {
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// Constant *C = cast<ConstantPoolSDNode>(N)->get();
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// SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
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// if (PICEnabled)
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// Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
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// else
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// Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
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// CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
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// return SDOperand(N, 0);
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assert(0 && "Constants are overrated");
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}
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
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CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA, getGlobalBaseReg());
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return SDOperand(N, 0);
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}
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case ISD::ExternalSymbol:
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CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
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CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
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CurDAG->getRegister(AlphaLowering.getVRegGP(), MVT::i64));
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return SDOperand(N, 0);
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case ISD::CALLSEQ_START:
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case ISD::CALLSEQ_END: {
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unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
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unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
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Alpha::ADJUSTSTACKDOWN : Alpha::ADJUSTSTACKUP;
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CurDAG->SelectNodeTo(N, Opc, MVT::Other,
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getI64Imm(Amt), Select(N->getOperand(0)));
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return SDOperand(N, 0);
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}
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case ISD::RET: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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if (N->getNumOperands() == 2) {
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SDOperand Val = Select(N->getOperand(1));
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if (N->getOperand(1).getValueType() == MVT::i64) {
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val);
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}
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}
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//BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
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// FIXME: add restoring of the RA to R26 to the chain
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// Finally, select this to a ret instruction.
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CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain);
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return SDOperand(N, 0);
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}
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}
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return SelectCode(Op);
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}
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SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
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SDNode *N = Op.Val;
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Addr = Select(N->getOperand(1));
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// unsigned CallOpcode;
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std::vector<SDOperand> CallOperands;
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std::vector<MVT::ValueType> TypeOperands;
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//grab the arguments
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for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
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TypeOperands.push_back(N->getOperand(i).getValueType());
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CallOperands.push_back(Select(N->getOperand(i)));
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}
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int count = N->getNumOperands() - 2;
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static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
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Alpha::R19, Alpha::R20, Alpha::R21};
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static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
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Alpha::F19, Alpha::F20, Alpha::F21};
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for (int i = 0; i < std::min(6, count); ++i) {
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if (MVT::isInteger(TypeOperands[i])) {
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Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i]);
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} else {
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assert(0 && "No FP support yet");
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}
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}
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assert(CallOperands.size() <= 6 && "Too big a call");
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr);
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// Finally, once everything is in registers to pass to the call, emit the
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// call itself.
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Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, Chain );
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std::vector<SDOperand> CallResults;
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switch (N->getValueType(0)) {
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default: assert(0 && "Unexpected ret value!");
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case MVT::Other: break;
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case MVT::i64:
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64).getValue(1);
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CallResults.push_back(Chain.getValue(0));
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break;
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}
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CallResults.push_back(Chain);
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for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
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CodeGenMap[Op.getValue(i)] = CallResults[i];
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return CallResults[Op.ResNo];
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}
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/// createAlphaISelDag - This pass converts a legalized DAG into a
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/// Alpha-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
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return new AlphaDAGToDAGISel(TM);
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}
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