Jyotsna Verma 1a35b8e2eb Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-10 20:27:34 +00:00
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AArch64
ARM
CPP
Generic
Hexagon	Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.	2013-05-10 20:27:34 +00:00
Inputs
MBlaze
Mips	[mips] Add instruction selection pattern for (seteq $LHS, 0).	2013-05-08 19:38:04 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX
PowerPC	Fix handling of anonymous aggregate parameters for powerpc*-apple-darwin8.	2013-05-08 17:22:33 +00:00
R600	R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns	2013-05-10 02:09:45 +00:00
SI
SPARC
SystemZ	[SystemZ] Add CodeGen test cases	2013-05-06 16:17:29 +00:00
Thumb
Thumb2
X86	DAGCombiner: Generate a correct constant for vector types when folding (xor (and)) into (and (not)).	2013-05-10 14:09:52 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00