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a35ce87e2e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15398 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.1 KiB
C++
64 lines
2.1 KiB
C++
//===- X86.td - Target definition file for the Intel X86 arch ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, refered to
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// here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "X86RegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "X86InstrInfo.td"
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def X86InstrInfo : InstrInfo {
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let PHIInst = PHI;
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// Define how we want to layout our TargetSpecific information field... This
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// should be kept up-to-date with the fields in the X86InstrInfo.h file.
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let TSFlagsFields = ["FormBits",
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"hasOpSizePrefix",
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"Prefix",
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"MemTypeBits",
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"ImmTypeBits",
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"FPFormBits",
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"printImplicitUsesAfter",
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"Opcode"];
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let TSFlagsShifts = [0,
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5,
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6,
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10,
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13,
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15,
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18,
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19];
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}
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def X86 : Target {
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// Specify the callee saved registers.
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let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
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// Yes, pointers are 32-bits in size.
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let PointerType = i32;
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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}
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