mirror of
https://github.com/c64scene-ar/llvm-6502.git
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da95a84a11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25120 91177308-0d34-0410-b5e6-96231b3b80d8
404 lines
13 KiB
C++
404 lines
13 KiB
C++
//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a DAG pattern matching instruction selector for X86,
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// converting from a legalized dag to a X86 dag.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86Subtarget.h"
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#include "X86ISelLowering.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Pattern Matcher Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
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/// SDOperand's instead of register numbers for the leaves of the matched
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/// tree.
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struct X86ISelAddressMode {
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enum {
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RegBase,
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FrameIndexBase,
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ConstantPoolBase
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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SDOperand Reg;
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int FrameIndex;
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} Base;
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unsigned Scale;
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SDOperand IndexReg;
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unsigned Disp;
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GlobalValue *GV;
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X86ISelAddressMode()
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0) {
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}
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};
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}
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namespace {
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Statistic<>
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NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
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//===--------------------------------------------------------------------===//
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/// ISel - X86 specific code to select X86 machine instructions for
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/// SelectionDAG operations.
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///
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class X86DAGToDAGISel : public SelectionDAGISel {
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/// ContainsFPCode - Every instruction we select that uses or defines a FP
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/// register should set this to true.
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bool ContainsFPCode;
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/// X86Lowering - This object fully describes how to lower LLVM code to an
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/// X86-specific SelectionDAG.
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X86TargetLowering X86Lowering;
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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public:
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X86DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(X86Lowering), X86Lowering(TM) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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}
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virtual const char *getPassName() const {
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return "X86 DAG->DAG Instruction Selection";
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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// Include the pieces autogenerated from the target description.
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#include "X86GenDAGISel.inc"
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private:
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SDOperand Select(SDOperand N);
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bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
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bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
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SDOperand &Scale, SDOperand &Index,
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SDOperand &Disp) {
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Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
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CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
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Scale = getI8Imm(AM.Scale);
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Index = AM.IndexReg;
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Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: getI32Imm(AM.Disp);
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}
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/// getI8Imm - Return a target constant with the specified value, of type
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/// i8.
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inline SDOperand getI8Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i8);
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}
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/// getI16Imm - Return a target constant with the specified value, of type
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/// i16.
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inline SDOperand getI16Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i16);
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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};
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}
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/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
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/// when it has created a SelectionDAG for us to codegen.
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void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Codegen the basic block.
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DAG.setRoot(Select(DAG.getRoot()));
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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/// FIXME: copied from X86ISelPattern.cpp
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode
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bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
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switch (N.getOpcode()) {
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default: break;
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case ISD::FrameIndex:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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AM.BaseType = X86ISelAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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}
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break;
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case ISD::ConstantPool:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N)) {
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AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
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AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32);
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return false;
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}
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}
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break;
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case ISD::GlobalAddress:
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case ISD::TargetGlobalAddress:
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if (AM.GV == 0) {
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AM.GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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return false;
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}
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break;
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case ISD::Constant:
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AM.Disp += cast<ConstantSDNode>(N)->getValue();
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return false;
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case ISD::SHL:
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if (AM.IndexReg.Val == 0 && AM.Scale == 1)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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unsigned Val = CN->getValue();
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if (Val == 1 || Val == 2 || Val == 3) {
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AM.Scale = 1 << Val;
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SDOperand ShVal = N.Val->getOperand(0);
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
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isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
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AM.IndexReg = ShVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(ShVal.Val->getOperand(1));
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AM.Disp += AddVal->getValue() << Val;
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} else {
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AM.IndexReg = ShVal;
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}
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return false;
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}
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}
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break;
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case ISD::MUL:
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// X*[3,5,9] -> X+X*[2,4,8]
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if (AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
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AM.Base.Reg.Val == 0)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
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if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
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AM.Scale = unsigned(CN->getValue())-1;
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SDOperand MulVal = N.Val->getOperand(0);
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SDOperand Reg;
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
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isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
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Reg = MulVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(MulVal.Val->getOperand(1));
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AM.Disp += AddVal->getValue() * CN->getValue();
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} else {
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Reg = N.Val->getOperand(0);
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}
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AM.IndexReg = AM.Base.Reg = Reg;
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return false;
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}
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break;
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case ISD::ADD: {
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X86ISelAddressMode Backup = AM;
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if (!MatchAddress(N.Val->getOperand(0), AM) &&
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!MatchAddress(N.Val->getOperand(1), AM))
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return false;
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AM = Backup;
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if (!MatchAddress(N.Val->getOperand(1), AM) &&
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!MatchAddress(N.Val->getOperand(0), AM))
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return false;
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AM = Backup;
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break;
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}
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}
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// Is the base register already occupied?
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if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
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// If so, check to see if the scale index register is set.
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if (AM.IndexReg.Val == 0) {
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AM.IndexReg = N;
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AM.Scale = 1;
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return false;
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}
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// Otherwise, we cannot select it.
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return true;
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}
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// Default, generate it as a register.
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AM.BaseType = X86ISelAddressMode::RegBase;
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AM.Base.Reg = N;
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return false;
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}
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/// SelectAddr - returns true if it is able pattern match an addressing mode.
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/// It returns the operands which make up the maximal addressing mode it can
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/// match by reference.
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bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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X86ISelAddressMode AM;
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if (!MatchAddress(N, AM)) {
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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if (AM.Base.Reg.Val)
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AM.Base.Reg = Select(AM.Base.Reg);
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else
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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}
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if (AM.IndexReg.Val)
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AM.IndexReg = Select(AM.IndexReg);
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else
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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getAddressOperands(AM, Base, Scale, Index, Disp);
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return true;
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}
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return false;
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}
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static bool isRegister0(SDOperand Op)
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{
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if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
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return (R->getReg() == 0);
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return false;
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}
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/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
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/// mode it matches can be cost effectively emitted as an LEA instruction.
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/// For X86, it always is unless it's just a (Reg + const).
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bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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X86ISelAddressMode AM;
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if (!MatchAddress(N, AM)) {
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bool SelectBase = false;
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bool SelectIndex = false;
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bool Check = false;
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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if (AM.Base.Reg.Val) {
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Check = true;
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SelectBase = true;
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} else {
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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}
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}
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if (AM.IndexReg.Val) {
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SelectIndex = true;
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} else {
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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}
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if (Check) {
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unsigned Complexity = 0;
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if (AM.Scale > 1)
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Complexity++;
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if (SelectIndex)
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Complexity++;
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if (AM.GV)
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Complexity++;
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else if (AM.Disp > 1)
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Complexity++;
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if (Complexity <= 1)
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return false;
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}
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if (SelectBase)
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AM.Base.Reg = Select(AM.Base.Reg);
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if (SelectIndex)
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AM.IndexReg = Select(AM.IndexReg);
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getAddressOperands(AM, Base, Scale, Index, Disp);
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return true;
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}
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return false;
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}
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SDOperand X86DAGToDAGISel::Select(SDOperand N) {
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SDNode *Node = N.Val;
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MVT::ValueType NVT = Node->getValueType(0);
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unsigned Opc;
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if (Node->getOpcode() >= ISD::BUILTIN_OP_END &&
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Node->getOpcode() < X86ISD::FIRST_NUMBER)
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return N; // Already selected.
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switch (Node->getOpcode()) {
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default: break;
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case ISD::TRUNCATE: {
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unsigned Reg;
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MVT::ValueType VT;
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switch (Node->getOperand(0).getValueType()) {
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default: assert(0 && "Unknown truncate!");
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case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
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case MVT::i32: Reg = X86::EAX; Opc = X86::MOV32rr; VT = MVT::i32; break;
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}
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SDOperand Tmp0 = Select(Node->getOperand(0));
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SDOperand Tmp1 = CurDAG->getTargetNode(Opc, VT, Tmp0);
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SDOperand InFlag = SDOperand(0,0);
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SDOperand Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(),
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Reg, Tmp1, InFlag).getValue(1);
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SDOperand Chain = Result.getValue(0);
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InFlag = Result.getValue(1);
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switch (NVT) {
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default: assert(0 && "Unknown truncate!");
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case MVT::i8: Reg = X86::AL; Opc = X86::MOV8rr; VT = MVT::i8; break;
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case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
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}
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Result = CurDAG->getCopyFromReg(Chain,
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Reg, VT, InFlag);
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return CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result);
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break;
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}
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}
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return SelectCode(N);
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}
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/// createX86ISelDag - This pass converts a legalized DAG into a
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/// X86-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createX86ISelDag(TargetMachine &TM) {
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return new X86DAGToDAGISel(TM);
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}
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